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mpm: apply linting to x4xx_rfdc_regs.py
This commit is contained in:
Max Köhler
Jörg Hofrichter
parent
894ecb691e
commit
be2e0a5c24
@ -8,45 +8,48 @@ X4xx RFDC register control
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"""
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import time
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from usrp_mpm.sys_utils.uio import UIO
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from usrp_mpm.chips.ic_reg_maps.x4xx_rfdc_regmap import x4xx_rfdc_regmap_t
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from usrp_mpm.mpmutils import poll_with_timeout
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from usrp_mpm.periph_manager.x4xx_clock_lookup import MMCM_LOCKGROUP_LOOKUP, MMCM_FILTERGROUP_LOOKUP
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from usrp_mpm.periph_manager.x4xx_clock_lookup import (
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MMCM_FILTERGROUP_LOOKUP,
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MMCM_LOCKGROUP_LOOKUP,
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)
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from usrp_mpm.sys_utils.uio import UIO
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# Number of ADCs and DACs in the RFDC.
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NUM_CONVERTERS = 16
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class RfdcRegsControl:
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"""
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Control the FPGA RFDC registers external to the XRFdc API
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"""
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mmcm_clock_map = {
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'prc': 0,
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'data_clk': 1,
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'data_clk_2x': 3,
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'rfdc_clk': 2,
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'rfdc_clk_x2': 4,
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"prc": 0,
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"data_clk": 1,
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"data_clk_2x": 3,
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"rfdc_clk": 2,
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"rfdc_clk_x2": 4,
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# These are synonymous to rfdc_clk
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'r0_clk': 2,
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'r0_clk_2x': 4,
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'r1_clk': 5,
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'r1_clk_2x': 6,
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"r0_clk": 2,
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"r0_clk_2x": 4,
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"r1_clk": 5,
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"r1_clk_2x": 6,
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}
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def __init__(self, label, log):
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self.log = log.getChild("RfdcRegs")
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self.regs = UIO(
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label=label,
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read_only=False
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)
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self.regs = UIO(label=label, read_only=False)
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self._regs = x4xx_rfdc_regmap_t()
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# All registers that we need to know the value of from the beginning we
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# need to read out here. Note that we can't yet read all registers when
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# this class is instantiated, as the RFDC itself is still being held in
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# reset. See also reset().
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self._update_reg('CAL_ENABLE_DB0_CHAN0')
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self._update_reg('FABRIC_DSP_INFO_BW')
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self._update_reg('RFDC_INFO_DB0_XTRA_RESAMP')
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self._update_reg("CAL_ENABLE_DB0_CHAN0")
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self._update_reg("FABRIC_DSP_INFO_BW")
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self._update_reg("RFDC_INFO_DB0_XTRA_RESAMP")
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for conv in range(NUM_CONVERTERS):
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self._update_reg("RFDC_INFO_BLOCK_MODE", conv)
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self._regs.save_state()
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@ -59,24 +62,28 @@ class RfdcRegsControl:
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Resets the state of the register object. Call this after pulling the
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RFDC out of reset.
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"""
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self._update_reg('CAL_ENABLE_DB0_CHAN0')
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self._update_reg('IQ_SWAP_DAC_DB0_CHAN0')
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self._update_reg('IQ_SWAP_DAC_DB1_CHAN0')
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self._update_reg("CAL_ENABLE_DB0_CHAN0")
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self._update_reg("IQ_SWAP_DAC_DB0_CHAN0")
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self._update_reg("IQ_SWAP_DAC_DB1_CHAN0")
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self._regs.save_state()
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def get_num_rx_channels(self):
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"""
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Returns the number of RX channels as defined in the RFDC register.
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"""
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return [getattr(self._regs, f'FABRIC_DSP_INFO_DB0_RX_CNT'),
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getattr(self._regs, f'FABRIC_DSP_INFO_DB1_RX_CNT')]
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return [
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getattr(self._regs, f"FABRIC_DSP_INFO_DB0_RX_CNT"),
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getattr(self._regs, f"FABRIC_DSP_INFO_DB1_RX_CNT"),
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]
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def get_num_tx_channels(self, board=0):
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"""
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Returns the number of TX channels as defined in the RFDC register.
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"""
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return [getattr(self._regs, f'FABRIC_DSP_INFO_DB0_TX_CNT'),
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getattr(self._regs, f'FABRIC_DSP_INFO_DB1_TX_CNT')]
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return [
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getattr(self._regs, f"FABRIC_DSP_INFO_DB0_TX_CNT"),
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getattr(self._regs, f"FABRIC_DSP_INFO_DB1_TX_CNT"),
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]
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def get_converter_mapping(self):
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"""
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@ -98,6 +105,7 @@ class RfdcRegsControl:
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This means there are 2 dboards. On the first dboard, we have 2 channels,
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and channel 0 uses tile 0, block 1.
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"""
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# define helper function to extract content from device memory
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def get_tuple(db, channel, is_adc):
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for i in range(NUM_CONVERTERS):
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@ -115,15 +123,11 @@ class RfdcRegsControl:
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raise ValueError(f"Could not find mapping for {db}, {channel}, {is_adc}")
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adc_mapping = tuple(
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tuple(
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get_tuple(db, chan, True) for chan in range(num_channels)
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)
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tuple(get_tuple(db, chan, True) for chan in range(num_channels))
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for db, num_channels in enumerate(self.get_num_rx_channels())
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)
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dac_mapping = tuple(
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tuple(
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get_tuple(db, chan, False) for chan in range(num_channels)
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)
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tuple(get_tuple(db, chan, False) for chan in range(num_channels))
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for db, num_channels in enumerate(self.get_num_tx_channels())
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)
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return adc_mapping, dac_mapping
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@ -134,15 +138,14 @@ class RfdcRegsControl:
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"""
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assert db_idx in (0, 1)
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return {
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'num_rx_chans': getattr(self._regs, f'FABRIC_DSP_INFO_DB{db_idx}_RX_CNT'),
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'num_tx_chans': getattr(self._regs, f'FABRIC_DSP_INFO_DB{db_idx}_TX_CNT'),
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'bw': self._regs.FABRIC_DSP_INFO_BW,
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'extra_resampling': getattr(self._regs, f'RFDC_INFO_DB{db_idx}_XTRA_RESAMP'),
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'spc_rx': 2**getattr(self._regs, f'RFDC_INFO_DB{db_idx}_SPC_RX'),
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'spc_tx': 2**getattr(self._regs, f'RFDC_INFO_DB{db_idx}_SPC_TX'),
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"num_rx_chans": getattr(self._regs, f"FABRIC_DSP_INFO_DB{db_idx}_RX_CNT"),
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"num_tx_chans": getattr(self._regs, f"FABRIC_DSP_INFO_DB{db_idx}_TX_CNT"),
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"bw": self._regs.FABRIC_DSP_INFO_BW,
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"extra_resampling": getattr(self._regs, f"RFDC_INFO_DB{db_idx}_XTRA_RESAMP"),
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"spc_rx": 2 ** getattr(self._regs, f"RFDC_INFO_DB{db_idx}_SPC_RX"),
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"spc_tx": 2 ** getattr(self._regs, f"RFDC_INFO_DB{db_idx}_SPC_TX"),
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}
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def get_threshold_status(self, db_idx, channel, threshold_idx):
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"""
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Retrieves the status bit for the given threshold block
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@ -178,16 +181,18 @@ class RfdcRegsControl:
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info = self.get_rfdc_info(db_idx)
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assert 0 <= channel < info["num_tx_chans"]
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assert enable in [False, True]
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setattr(self._regs, f'CAL_ENABLE_DB{db_idx}_CHAN{channel}', int(enable))
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setattr(self._regs, f"CAL_ENABLE_DB{db_idx}_CHAN{channel}", int(enable))
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self._commit()
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def enable_iq_swap(self, enable, db_id, chan_idx, is_dac):
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assert db_id in (0, 1)
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num_channels = self.get_num_tx_channels()[db_id] if is_dac else self.get_num_rx_channels()[db_id]
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num_channels = (
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self.get_num_tx_channels()[db_id] if is_dac else self.get_num_rx_channels()[db_id]
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)
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assert chan_idx in range(num_channels)
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assert int(is_dac) in (0, 1)
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addr_name = f'IQ_SWAP_{"DAC" if is_dac else "ADC"}_DB{db_id}_CHAN{chan_idx}'
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enum_name = addr_name + '_t'
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enum_name = addr_name + "_t"
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setattr(self._regs, addr_name, getattr(self._regs, enum_name)(enable))
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self._commit()
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@ -198,10 +203,11 @@ class RfdcRegsControl:
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"""
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Put MMCM into reset, or take it out of reset
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"""
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self._regs.MMCM_RESET = \
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self._regs.MMCM_RESET_t.MMCM_RESET_ENABLE \
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if reset \
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self._regs.MMCM_RESET = (
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self._regs.MMCM_RESET_t.MMCM_RESET_ENABLE
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if reset
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else self._regs.MMCM_RESET_t.MMCM_RESET_DISABLE
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)
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self._commit()
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def reconfigure_mmcm(self, use_regs=True):
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@ -222,9 +228,10 @@ class RfdcRegsControl:
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# poke directly instead.
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self._poke(
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self._regs.get_addr("MMCM_LOAD_SEN"),
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self._regs.get_reg(self._regs.get_addr("MMCM_LOAD_SEN")))
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self._regs.get_reg(self._regs.get_addr("MMCM_LOAD_SEN")),
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)
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self.log.trace('MMCM Configuration applied, now waiting for MMCM to lock...')
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self.log.trace("MMCM Configuration applied, now waiting for MMCM to lock...")
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self.wait_for_mmcm_drp_done()
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self.clear_data_clk_unlocked()
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self._commit()
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@ -236,9 +243,9 @@ class RfdcRegsControl:
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removed when this is resolved in digital.
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"""
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time.sleep(1)
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self._regs.CLEAR_DATA_CLK_UNLOCKED=self._regs.CLEAR_DATA_CLK_UNLOCKED_t(1)
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self._regs.CLEAR_DATA_CLK_UNLOCKED = self._regs.CLEAR_DATA_CLK_UNLOCKED_t(1)
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self._commit()
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self._regs.CLEAR_DATA_CLK_UNLOCKED=self._regs.CLEAR_DATA_CLK_UNLOCKED_t(0)
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self._regs.CLEAR_DATA_CLK_UNLOCKED = self._regs.CLEAR_DATA_CLK_UNLOCKED_t(0)
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self._commit()
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def wait_for_mmcm_locked(self, timeout=0.001):
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@ -247,12 +254,14 @@ class RfdcRegsControl:
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The datasheet specifies a 100us max lock time
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"""
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self.wait_for_mmcm_drp_done()
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def check_lock():
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self._update_reg('MMCM_LOCKED')
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self._update_reg("MMCM_LOCKED")
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if self._regs.MMCM_LOCKED:
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self.log.trace("RF MMCM lock detected.")
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return True
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return False
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poll_sleep_ms = 0.2
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if not poll_with_timeout(check_lock, timeout * 1000, poll_sleep_ms):
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self.log.error("MMCM failed to lock in the expected time.")
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@ -271,11 +280,12 @@ class RfdcRegsControl:
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# of the MMCM, so we'll check this bit is also de-asserted, which it
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# should be according to pg065.
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poll_sleep_ms = 0.2
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def check_reconfig_done():
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self._update_reg('MMCM_LOAD_SEN')
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self._update_reg("MMCM_LOAD_SEN")
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return not self._regs.MMCM_LOAD_SEN
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if not poll_with_timeout(
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check_reconfig_done, timeout * 1000, poll_sleep_ms):
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if not poll_with_timeout(check_reconfig_done, timeout * 1000, poll_sleep_ms):
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self.log.error("MMCM failed to confirm DRP in the expected time.")
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raise RuntimeError("MMCM failed to confirm DRP in the expected time.")
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# We need to tell the reg cache that the value changed back:
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@ -308,12 +318,12 @@ class RfdcRegsControl:
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self._regs.MMCM_DIV_HI_TIME = 0
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self._regs.MMCM_DIV_NO_COUNT = 1
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self._regs.MMCM_DIV_EDGE = 0
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elif div_val % 2: # Odd divisions
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elif div_val % 2: # Odd divisions
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self._regs.MMCM_DIV_LO_TIME = div_val_by_2 + 1
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self._regs.MMCM_DIV_HI_TIME = div_val_by_2
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self._regs.MMCM_DIV_NO_COUNT = 0
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self._regs.MMCM_DIV_EDGE = 1
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else: # Even divisions
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else: # Even divisions
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self._regs.MMCM_DIV_LO_TIME = div_val_by_2
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self._regs.MMCM_DIV_HI_TIME = div_val_by_2
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self._regs.MMCM_DIV_NO_COUNT = 0
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@ -331,42 +341,43 @@ class RfdcRegsControl:
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Does not commit register values!
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"""
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assert clock_name in self.mmcm_clock_map \
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or (isinstance(clock_name, int) and 0 <= clock_name <= 6)
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clock_idx = clock_name if isinstance(clock_name, int) \
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else self.mmcm_clock_map.get(clock_name)
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assert clock_name in self.mmcm_clock_map or (
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isinstance(clock_name, int) and 0 <= clock_name <= 6
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)
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clock_idx = (
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clock_name if isinstance(clock_name, int) else self.mmcm_clock_map.get(clock_name)
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)
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div_val_int = int(div_val)
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assert 1 <= div_val_int <= 128
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div_val_int_by2 = div_val_int // 2
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div_val_frac = div_val - div_val_int
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assert div_val_frac == 0.0 or \
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(clock_idx == 0 and ((div_val_frac / 0.125) % 1 == 0))
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assert div_val_frac == 0.0 or (clock_idx == 0 and ((div_val_frac / 0.125) % 1 == 0))
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if div_val_int == 1:
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setattr(self._regs, f'CLKOUT{clock_idx}_LO_TIME', 0)
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setattr(self._regs, f'CLKOUT{clock_idx}_HI_TIME', 0)
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setattr(self._regs, f'CLKOUT{clock_idx}_NO_COUNT', 1)
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setattr(self._regs, f'CLKOUT{clock_idx}_EDGE', 0)
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setattr(self._regs, f"CLKOUT{clock_idx}_LO_TIME", 0)
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setattr(self._regs, f"CLKOUT{clock_idx}_HI_TIME", 0)
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setattr(self._regs, f"CLKOUT{clock_idx}_NO_COUNT", 1)
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setattr(self._regs, f"CLKOUT{clock_idx}_EDGE", 0)
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elif div_val_int == 128:
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# The 128 case is undocumented in pg065 and xapp888, but the MMCM
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# does have a documented max division of 128, and a division value
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# of 0 is invalid so it can be used for this case. This was confirmed
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# by setting the division to 128 in the clock wizard GUI and reading
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# out the resulting register value.
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setattr(self._regs, f'CLKOUT{clock_idx}_LO_TIME', 0)
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setattr(self._regs, f'CLKOUT{clock_idx}_HI_TIME', 0)
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setattr(self._regs, f'CLKOUT{clock_idx}_NO_COUNT', 0)
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setattr(self._regs, f'CLKOUT{clock_idx}_EDGE', 0)
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elif div_val_int % 2: # Odd divisions
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setattr(self._regs, f'CLKOUT{clock_idx}_LO_TIME', div_val_int_by2 + 1)
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setattr(self._regs, f'CLKOUT{clock_idx}_HI_TIME', div_val_int_by2)
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setattr(self._regs, f'CLKOUT{clock_idx}_NO_COUNT', 0)
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setattr(self._regs, f'CLKOUT{clock_idx}_EDGE', 1)
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else: # Even divisions
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setattr(self._regs, f'CLKOUT{clock_idx}_LO_TIME', div_val_int_by2)
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setattr(self._regs, f'CLKOUT{clock_idx}_HI_TIME', div_val_int_by2)
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setattr(self._regs, f'CLKOUT{clock_idx}_NO_COUNT', 0)
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setattr(self._regs, f'CLKOUT{clock_idx}_EDGE', 0)
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setattr(self._regs, f'CLKOUT{clock_idx}_MX', 0)
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setattr(self._regs, f"CLKOUT{clock_idx}_LO_TIME", 0)
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setattr(self._regs, f"CLKOUT{clock_idx}_HI_TIME", 0)
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setattr(self._regs, f"CLKOUT{clock_idx}_NO_COUNT", 0)
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setattr(self._regs, f"CLKOUT{clock_idx}_EDGE", 0)
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elif div_val_int % 2: # Odd divisions
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setattr(self._regs, f"CLKOUT{clock_idx}_LO_TIME", div_val_int_by2 + 1)
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setattr(self._regs, f"CLKOUT{clock_idx}_HI_TIME", div_val_int_by2)
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setattr(self._regs, f"CLKOUT{clock_idx}_NO_COUNT", 0)
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setattr(self._regs, f"CLKOUT{clock_idx}_EDGE", 1)
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else: # Even divisions
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setattr(self._regs, f"CLKOUT{clock_idx}_LO_TIME", div_val_int_by2)
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setattr(self._regs, f"CLKOUT{clock_idx}_HI_TIME", div_val_int_by2)
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setattr(self._regs, f"CLKOUT{clock_idx}_NO_COUNT", 0)
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setattr(self._regs, f"CLKOUT{clock_idx}_EDGE", 0)
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setattr(self._regs, f"CLKOUT{clock_idx}_MX", 0)
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if clock_idx == 0:
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div_val_frac_code = int(div_val_frac / 0.125)
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self._regs.CLKOUT0_FRAC_EN = int(div_val_frac != 0)
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@ -384,15 +395,17 @@ class RfdcRegsControl:
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For clock_name, see set_mmcm_output_div().
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"""
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assert clock_name in self.mmcm_clock_map \
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or (isinstance(clock_name, int) and 0 <= clock_name <= 6)
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clock_idx = clock_name if isinstance(clock_name, int) \
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else self.mmcm_clock_map.get(clock_name)
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self._update_reg(f'CLKOUT{clock_idx}_LO_TIME')
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self._update_reg(f'CLKOUT{clock_idx}_NO_COUNT')
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lo_time = getattr(self._regs, f'CLKOUT{clock_idx}_LO_TIME')
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hi_time = getattr(self._regs, f'CLKOUT{clock_idx}_HI_TIME')
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no_count = getattr(self._regs, f'CLKOUT{clock_idx}_NO_COUNT')
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assert clock_name in self.mmcm_clock_map or (
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isinstance(clock_name, int) and 0 <= clock_name <= 6
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)
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clock_idx = (
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clock_name if isinstance(clock_name, int) else self.mmcm_clock_map.get(clock_name)
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)
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self._update_reg(f"CLKOUT{clock_idx}_LO_TIME")
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self._update_reg(f"CLKOUT{clock_idx}_NO_COUNT")
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lo_time = getattr(self._regs, f"CLKOUT{clock_idx}_LO_TIME")
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hi_time = getattr(self._regs, f"CLKOUT{clock_idx}_HI_TIME")
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no_count = getattr(self._regs, f"CLKOUT{clock_idx}_NO_COUNT")
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div_val = 1 if no_count else lo_time + hi_time
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if div_val == 0:
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div_val = 128
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@ -416,12 +429,12 @@ class RfdcRegsControl:
|
||||
self._regs.CLKFBOUT_HI_TIME = 0
|
||||
self._regs.CLKFBOUT_NO_COUNT = 1
|
||||
self._regs.CLKFBOUT_EDGE = 0
|
||||
elif div_val_int % 2: # Odd divisions
|
||||
elif div_val_int % 2: # Odd divisions
|
||||
self._regs.CLKFBOUT_LO_TIME = div_val_int_by2 + 1
|
||||
self._regs.CLKFBOUT_HI_TIME = div_val_int_by2
|
||||
self._regs.CLKFBOUT_NO_COUNT = 0
|
||||
self._regs.CLKFBOUT_EDGE = 1
|
||||
else: # Even divisions
|
||||
else: # Even divisions
|
||||
self._regs.CLKFBOUT_LO_TIME = div_val_int_by2
|
||||
self._regs.CLKFBOUT_HI_TIME = div_val_int_by2
|
||||
self._regs.CLKFBOUT_NO_COUNT = 0
|
||||
@ -438,8 +451,8 @@ class RfdcRegsControl:
|
||||
|
||||
# Fetch the register values from LUTs.
|
||||
# LUTs' first index corresponds to FB_DIV = 1
|
||||
lock_lookup = MMCM_LOCKGROUP_LOOKUP[div_val-1]
|
||||
filt_lookup = MMCM_FILTERGROUP_LOOKUP[div_val-1]
|
||||
lock_lookup = MMCM_LOCKGROUP_LOOKUP[div_val - 1]
|
||||
filt_lookup = MMCM_FILTERGROUP_LOOKUP[div_val - 1]
|
||||
|
||||
# Lock lookup distribution (from XAPP888):
|
||||
# LOCKREG1[9:0] = lock_lookup[29:20]
|
||||
@ -449,11 +462,13 @@ class RfdcRegsControl:
|
||||
# LOCKREG3[9:0] = lock_lookup[19:10]
|
||||
self._regs.MMCM_LOCKREG1 = (lock_lookup & 0x003FF00000) >> 20
|
||||
|
||||
self._regs.MMCM_LOCKREG2 = (lock_lookup & 0x00000003FF) >> 0 | \
|
||||
(lock_lookup & 0x07C0000000) >> (30-10)
|
||||
self._regs.MMCM_LOCKREG2 = (lock_lookup & 0x00000003FF) >> 0 | (
|
||||
lock_lookup & 0x07C0000000
|
||||
) >> (30 - 10)
|
||||
|
||||
self._regs.MMCM_LOCKREG3 = (lock_lookup & 0x00000FFC00) >> 10 | \
|
||||
(lock_lookup & 0xF800000000) >> (35-10)
|
||||
self._regs.MMCM_LOCKREG3 = (lock_lookup & 0x00000FFC00) >> 10 | (
|
||||
lock_lookup & 0xF800000000
|
||||
) >> (35 - 10)
|
||||
|
||||
# Filter lookup distribution (from XAPP888):
|
||||
# FILTREG1[15] = filt_lookup[9]
|
||||
@ -463,14 +478,18 @@ class RfdcRegsControl:
|
||||
# FILTREG2[12:11] = filt_lookup[4:3]
|
||||
# FILTREG2[8:7] = filt_lookup[2:1]
|
||||
# FILTREG2[4] = filt_lookup[4]
|
||||
self._regs.MMCM_FILTREG1 = (filt_lookup & 0x200) << (15 - 9) | \
|
||||
(filt_lookup & 0x180) << (11 - 7) | \
|
||||
(filt_lookup & 0x4) << ( 8 - 6)
|
||||
self._regs.MMCM_FILTREG1 = (
|
||||
(filt_lookup & 0x200) << (15 - 9)
|
||||
| (filt_lookup & 0x180) << (11 - 7)
|
||||
| (filt_lookup & 0x4) << (8 - 6)
|
||||
)
|
||||
|
||||
self._regs.MMCM_FILTREG2 = (filt_lookup & 0x20) << (15 - 5) | \
|
||||
(filt_lookup & 0x18) << (11 - 3) | \
|
||||
(filt_lookup & 0x6) << ( 7 - 1) | \
|
||||
(filt_lookup & 0x1) << ( 4 - 0)
|
||||
self._regs.MMCM_FILTREG2 = (
|
||||
(filt_lookup & 0x20) << (15 - 5)
|
||||
| (filt_lookup & 0x18) << (11 - 3)
|
||||
| (filt_lookup & 0x6) << (7 - 1)
|
||||
| (filt_lookup & 0x1) << (4 - 0)
|
||||
)
|
||||
self._commit()
|
||||
|
||||
def set_gated_clock_enables(self, value=True):
|
||||
@ -479,77 +498,65 @@ class RfdcRegsControl:
|
||||
|
||||
This disables/enables the clock buffers on the MMCM.
|
||||
"""
|
||||
self._regs.RF_PLL_ENABLE_DATA_CLK = \
|
||||
self._regs.RF_PLL_ENABLE_DATA_CLK_t(int(value))
|
||||
self._regs.RF_PLL_ENABLE_DATA_CLK_x2 = \
|
||||
self._regs.RF_PLL_ENABLE_DATA_CLK_x2_t(int(value))
|
||||
self._regs.RF_PLL_ENABLE_RF0_CLK = \
|
||||
self._regs.RF_PLL_ENABLE_RF0_CLK_t(int(value))
|
||||
self._regs.RF_PLL_ENABLE_RF0_CLK_x2 = \
|
||||
self._regs.RF_PLL_ENABLE_RF0_CLK_x2_t(int(value))
|
||||
self._regs.RF_PLL_ENABLE_RF1_CLK = \
|
||||
self._regs.RF_PLL_ENABLE_RF1_CLK_t(int(value))
|
||||
self._regs.RF_PLL_ENABLE_RF1_CLK_x2 = \
|
||||
self._regs.RF_PLL_ENABLE_RF1_CLK_x2_t(int(value))
|
||||
self._regs.RF_PLL_ENABLE_DATA_CLK = self._regs.RF_PLL_ENABLE_DATA_CLK_t(int(value))
|
||||
self._regs.RF_PLL_ENABLE_DATA_CLK_x2 = self._regs.RF_PLL_ENABLE_DATA_CLK_x2_t(int(value))
|
||||
self._regs.RF_PLL_ENABLE_RF0_CLK = self._regs.RF_PLL_ENABLE_RF0_CLK_t(int(value))
|
||||
self._regs.RF_PLL_ENABLE_RF0_CLK_x2 = self._regs.RF_PLL_ENABLE_RF0_CLK_x2_t(int(value))
|
||||
self._regs.RF_PLL_ENABLE_RF1_CLK = self._regs.RF_PLL_ENABLE_RF1_CLK_t(int(value))
|
||||
self._regs.RF_PLL_ENABLE_RF1_CLK_x2 = self._regs.RF_PLL_ENABLE_RF1_CLK_x2_t(int(value))
|
||||
self._commit()
|
||||
|
||||
def set_reset_adc_dac_chains(self, reset=True):
|
||||
""" Resets or enables the ADC and DAC chain for the given dboard """
|
||||
"""Resets or enables the ADC and DAC chain for the given dboard"""
|
||||
if not reset:
|
||||
# We actually don't keep the converters in reset, so this is a no-op.
|
||||
self._converter_chains_in_reset = False
|
||||
return
|
||||
if self._converter_chains_in_reset:
|
||||
self.log.debug('Converters are already in reset. '
|
||||
'The reset bit will NOT be toggled.')
|
||||
self.log.debug("Converters are already in reset. " "The reset bit will NOT be toggled.")
|
||||
return
|
||||
|
||||
# The actual reset procedure
|
||||
def _check_for_done(db_idx, xdc):
|
||||
""" Query a specified done bit. 'xdc' must be either 'ADC' or 'DAC. """
|
||||
assert xdc in ('ADC', 'DAC')
|
||||
"""Query a specified done bit. 'xdc' must be either 'ADC' or 'DAC."""
|
||||
assert xdc in ("ADC", "DAC")
|
||||
assert db_idx in (0, 1)
|
||||
reg_name = f'RFDC_DB{db_idx}_{xdc}_RESET_DONE'
|
||||
reg_name = f"RFDC_DB{db_idx}_{xdc}_RESET_DONE"
|
||||
self._update_reg(reg_name)
|
||||
return getattr(self._regs, reg_name)
|
||||
|
||||
reset_timeout = 5000 # ms
|
||||
poll_sleep = 1 # ms
|
||||
reset_timeout = 5000 # ms
|
||||
poll_sleep = 1 # ms
|
||||
|
||||
def poll_for_done(db_idx, xdc):
|
||||
""" Shorthand for poll_with_timeout on the DONE bits """
|
||||
"""Shorthand for poll_with_timeout on the DONE bits"""
|
||||
return poll_with_timeout(
|
||||
lambda: _check_for_done(db_idx, xdc), reset_timeout, poll_sleep)
|
||||
lambda: _check_for_done(db_idx, xdc), reset_timeout, poll_sleep
|
||||
)
|
||||
|
||||
# Reset the ADC chains
|
||||
self.log.trace('Resetting ADC chain')
|
||||
self._regs.RFDC_DB0_ADC_RESET = \
|
||||
self._regs.RFDC_DB0_ADC_RESET_t.RFDC_DB0_ADC_RESET_ENABLE
|
||||
self._regs.RFDC_DB1_ADC_RESET = \
|
||||
self._regs.RFDC_DB1_ADC_RESET_t.RFDC_DB1_ADC_RESET_ENABLE
|
||||
self.log.trace("Resetting ADC chain")
|
||||
self._regs.RFDC_DB0_ADC_RESET = self._regs.RFDC_DB0_ADC_RESET_t.RFDC_DB0_ADC_RESET_ENABLE
|
||||
self._regs.RFDC_DB1_ADC_RESET = self._regs.RFDC_DB1_ADC_RESET_t.RFDC_DB1_ADC_RESET_ENABLE
|
||||
self._commit()
|
||||
for db_idx in (0, 1):
|
||||
if not poll_for_done(db_idx, 'ADC'):
|
||||
self.log.error("Timeout while resetting ADC chains.")
|
||||
raise RuntimeError("Timeout while resetting ADC chains.")
|
||||
self._regs.RFDC_DB0_ADC_RESET = \
|
||||
self._regs.RFDC_DB0_ADC_RESET_t.RFDC_DB0_ADC_RESET_DISABLE
|
||||
self._regs.RFDC_DB1_ADC_RESET = \
|
||||
self._regs.RFDC_DB1_ADC_RESET_t.RFDC_DB1_ADC_RESET_DISABLE
|
||||
if not poll_for_done(db_idx, "ADC"):
|
||||
self.log.error("Timeout while resetting ADC chains.")
|
||||
raise RuntimeError("Timeout while resetting ADC chains.")
|
||||
self._regs.RFDC_DB0_ADC_RESET = self._regs.RFDC_DB0_ADC_RESET_t.RFDC_DB0_ADC_RESET_DISABLE
|
||||
self._regs.RFDC_DB1_ADC_RESET = self._regs.RFDC_DB1_ADC_RESET_t.RFDC_DB1_ADC_RESET_DISABLE
|
||||
self._commit()
|
||||
# Reset the DAC chains
|
||||
self.log.trace('Resetting DAC chain')
|
||||
self._regs.RFDC_DB0_DAC_RESET = \
|
||||
self._regs.RFDC_DB0_DAC_RESET_t.RFDC_DB0_DAC_RESET_ENABLE
|
||||
self._regs.RFDC_DB1_DAC_RESET = \
|
||||
self._regs.RFDC_DB1_DAC_RESET_t.RFDC_DB1_DAC_RESET_ENABLE
|
||||
self.log.trace("Resetting DAC chain")
|
||||
self._regs.RFDC_DB0_DAC_RESET = self._regs.RFDC_DB0_DAC_RESET_t.RFDC_DB0_DAC_RESET_ENABLE
|
||||
self._regs.RFDC_DB1_DAC_RESET = self._regs.RFDC_DB1_DAC_RESET_t.RFDC_DB1_DAC_RESET_ENABLE
|
||||
self._commit()
|
||||
for db_idx in (0, 1):
|
||||
if not poll_for_done(db_idx, 'DAC'):
|
||||
self.log.error("Timeout while resetting DAC chains.")
|
||||
raise RuntimeError("Timeout while resetting DAC chains.")
|
||||
self._regs.RFDC_DB0_DAC_RESET = \
|
||||
self._regs.RFDC_DB0_DAC_RESET_t.RFDC_DB0_DAC_RESET_DISABLE
|
||||
self._regs.RFDC_DB1_DAC_RESET = \
|
||||
self._regs.RFDC_DB1_DAC_RESET_t.RFDC_DB1_DAC_RESET_DISABLE
|
||||
if not poll_for_done(db_idx, "DAC"):
|
||||
self.log.error("Timeout while resetting DAC chains.")
|
||||
raise RuntimeError("Timeout while resetting DAC chains.")
|
||||
self._regs.RFDC_DB0_DAC_RESET = self._regs.RFDC_DB0_DAC_RESET_t.RFDC_DB0_DAC_RESET_DISABLE
|
||||
self._regs.RFDC_DB1_DAC_RESET = self._regs.RFDC_DB1_DAC_RESET_t.RFDC_DB1_DAC_RESET_DISABLE
|
||||
self._commit()
|
||||
self._converter_chains_in_reset = True
|
||||
|
||||
@ -557,7 +564,7 @@ class RfdcRegsControl:
|
||||
"""
|
||||
Debugging API to dump the RFDC interface status.
|
||||
"""
|
||||
self._update_reg('STATUS_RFDC_DB0_DAC_TREADY')
|
||||
self._update_reg("STATUS_RFDC_DB0_DAC_TREADY")
|
||||
# pylint: disable=f-string-without-interpolation
|
||||
# pylint: disable=invalid-name
|
||||
r = self._regs
|
||||
@ -590,12 +597,12 @@ class RfdcRegsControl:
|
||||
# Internal helpers
|
||||
###########################################################################
|
||||
def _poke(self, addr, val):
|
||||
""" Shorthand for self.regs.poke32 """
|
||||
"""Shorthand for self.regs.poke32"""
|
||||
with self.regs:
|
||||
self.regs.poke32(addr, val)
|
||||
|
||||
def _peek(self, addr):
|
||||
""" Shorthand for self.regs.peek32 """
|
||||
"""Shorthand for self.regs.peek32"""
|
||||
with self.regs:
|
||||
result = self.regs.peek32(addr)
|
||||
return result
|
||||
|
||||
Loading…
Reference in New Issue
Block a user