Use --seed only to initialize a local deterministic random number
generator. Generate a new signed 32-bit BUILD_SEED for each FPGA build
attempt instead of passing --seed directly to the first build. This
avoids accidentally using sequential pipeline attempt numbers as
BUILD_SEED values.
Using the same --seed produces the same BUILD_SEED sequence, preserving
reproducibility.
Added variants for the DDC/DUC blocks that can process multiple
samples per cycle and can be used for bandwidths higher than
200Mhz.
This new feature is integrated into the existing RFNoC DDC/DUC
blocks. Depending on the Radio bandwidth specified for the USRP
variant, the DxC blocks will instantiate the existing singlesample
implementation(for FPGA image variants <= 200MHz) or instantiate
the multisample implementation(for FPGA image variants > 200MHz).
Co-authored-by: Niels Garibaldi <niels.steffen.garibaldi@emerson.com>
Co-authored-by: André Zoch <andre.zoch@emerson.com>
Co-authored-by: Meghana Halladamath <meghana.halladamath@emerson.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Max Köhler <max.koehler@emerson.com>
Replacing the synth target of the FPGA Makefiles with the normal "bin" flow
which ends after synthesis if desired. This aligns the build flows in case ILAs
want to be added.
This adds support for the new USRP X420. It is the latest addition to
our X4xx series and comes with two HBX daughterboards. The HBX is
a one-channel direct conversion transceiver that covers 5G NR FR3 and
X-/KU-Band needs for Research and Prototyping in a frequency range of 10
MHz up to 20 GHz. It supports analog bandwidths of up to 1 GHz.
This commit is the FPGA portion of the X420 support.
Co-authored-by: Markus Schill <markus.schill@emerson.com>
Use a resources file to pass RFNoC OOT source files to Vivado TCL
scripts, avoiding ARG_MAX argument list limits.
Co-authored-by: Martin Braun <martin.braun@ettus.com>
The version check causes an error in Vivado that prevents the use of
JTAG/debug when users have a patch installed. This disables the error,
but it will still give a warning in case they really do have a
legitimate mismatch. This change fixes the issue when users use our
tooling to launch a build in the GUI then launch the hardware manager,
but it may still occur if they launch the GUI themselves outside of our
tooling.
This change sets StdArithNoWarnings and NumericStdNoWarnings by
default for ModelSim simulations. Without this, an excessive number of
warnings can be generated by Xilinx IP during simulation.
This changes the -onfinish setting from "stop" to "final" for Questa
and ModelSim. The "final" setting is required so that SystemVerilog
final blocks run. This also has the same effect as "stop" in that it
won't ask you in the GUI if you want to exit the simulator when
$finish() is called.
This commit addresses several issues that can occur with different
simulators. It changes the following:
- Update documentation
- Ignore testbenches in build-ip folders
- Tolerate extra lines in the testbench results regular expression
- Match numbers using \d instead of + to avoid ValueError exceptions
- Only fetch the start_time if it exists
- Allow any simulator make target (don't limit it to specific choices)
This reverts commit e572bab3ee.
The problem with skipping the "unnecessary" bash wrappers is that Ubuntu
systems use 'dash' as a default shell, which does not support our build
infrastructure. While we do recommend not using dash for building FPGA
builds in our documentation, it's not obvious that dash is the problem
when calling rfnoc_image_builder.
This Python utility was getting a bit rotten. The following updates
where made:
- Reformatted using ni-python-styleguide
- Fixed formatting of regex strings by declaring them 'raw'
- Updated docstrings and any linter issues
On Pyton 3.12 and beyond, this will no longer throw SyntaxError
warnings.
Previously, the build tools for the FPGA bitfiles would try and
autodetect the Vivado executable, but would allow for a `vivado_lab`
executable. However, Vivado Lab Edition can't build bitfiles nor run
testbenches. Its only use with the USRP FPGA build tooling is to run
`viv_jtag_program` and `viv_jtag_list` (which are command-line proxies
for probing FPGAs attached to JTAG, and for programming bitfiles over
JTAG, e.g. to an X3x0).
When Vivado Lab and Vivado were present, it was possible that we ran
into issues where Vivado Labs would be preferred, and then builds or
testbenches would fail.
We therefore remove the ability to use Vivado Lab. Running the Vivado
Lab Edition with the GUI, and loading and probing bitfiles is of course
still possible, but tools like `rfnoc_image_builder` can no longer
accidentally try to use Vivado Lab instead of regular Vivado.
