This inherits RuntimeError and saves from logging and throwing in
separate steps. Instead of
```python
log.error("Error X occured!")
raise RuntimeError("Error X occured!")
```
do
```python
raise LogRuntimeError(log, "Error X occured!")
```
This demotes the sync_tiles() error to a warning to be consistent with
what the code does. We only raise a RuntimeError if the tile latencies
are not equal for all tiles, which is a little bit later. This is where
an error log was added now.
sync_tiles() may fail with some rare user configurations but it won't
make the device unusable for all use-cases. Therefore a warning is okay
in that place while bad latencies lead to an error.
This changes the clock-configuration order of operations such that all
SPLL-related settings are applied first (including syncing R-dividers to
PPS), and only then are MMCM and RFDC configured.
Previously, syncing R-dividers would happen after everything was
configured.
This adds an updateable_components overridable dictionary into the
daughterboards base class.
On X410, because some of the FPGA compatibility stems from DB-specific
components, they are moved into class ZBX.
New warning informs user if a tune_request requests lo_offset
and rfnoc device does not contain DSP to apply this request.
Additionally the requestsed lo_offset is ignored and the radio
is tuned to the target frequency (fe_freq + offset_freq).
This change fixes issues with the reset strategy for devices that don't
use default clocking parameters. That used to cause issues when
restarting the tiles and made those devices have some bigger variations
in power measurements. For X410 this should not change the behavior
compared to uhd master.
Extended get/set_time_* implementations to support multiple
timekeepers running at the same clock rates.
Puplic get function now use private implementations that are
aware of multiple timekeepers and continue to check only for
tk 0.
Public set functions were extended to update all timekeepers
to a similar timespec. This best effort may still result in
some asynch variance.
The function set_time_unknown_pps was extended to verify all
time registers, incl. multiple TK per mboard. This
verification code is very similar, but less sophisticated
then code found in mb_controller::synchronize >> sync_tks
and may take a long time if many devices are in the same
MultiUsrp session.
Changes were made in response to X440 test failure for test
failure on ch 4 in test test_examples_txrx_loopback_to_file.
The filter for the IF is centered at 2440 MHz with a bandwidth of 84
MHz. This means that the LO for the IF is in the pass band for
frequencies under 42 MHz. The IF was being shifted 60 MHz for
frequencies under 100 MHz, but this was causing distortion in the filter
response from being too close to the filter edge. This change shifts
the IF for frequencies under 42 MHz such that the LO is at the edge of
the pass band and uses the standard 2440 MHz IF for frequencies between
42 MHz and 100 MHz.
Signed-off-by: michael-west <michael.west@ettus.com>
This adds X4xxRfdcCtrl.reset_tiles(), which resets all enabled tiles and
sets their registers and settings back to initial defaults. The same
functionality was previously implemented in reset_rfdc(), but we want to
be able to reset the RFDC clocks without clearing all registers.
During device initialization, however, we retain this reset of all tiles
by modifying the initialization sequence.
Before this change, we indiscriminately first set the sync source in
init(), then the master clock rate again (it is already set in
set_sync_source(), albeit to a potentially older value).
This adds checks to the args to see if things have actually changed, and
sets all settings in one go.
FPGA:
- Split up MB registers that control daughterboard specific settings so
that daughterboards 0 and 1 could have different setings, in
preparation for future devices that require different settings.
This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
block/tile mapping of the individual channels, and information about
resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
them to their own headers, so it's trivial to add device-specific
sections of code instead for other devices in the future.
- This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
was unused and possibly broken.
- Move daughterboard-specific code into its own code location
(dboards/zbx)
- Move X410-specific register documentation to its own location
(doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
timekeeper)
MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Introduces the following changes:
- When mb_controller::synchronize() is called, *all* timekeepers are
synchronized to the same PPS, not just the first one
- On failure, logging prints the TK index as well as the motherboard
index
- If a single motherboard is initialized, we also check for multiple
timekeepers, and if more than one timekeeper is present, we do
a regular synchronization on that device to internal PPS instead
of simply resetting the timekeeper to zero.
- If multiple boards with multiple timekeepers each are initialized in
a session with unsynchronized USRPs (e.g., the 'internal' clock source
is used) then we make sure that timekeepers within a motherboard are
still synchronous.
Co-authored-by: Marian Koop <marian.koop@ni.com>
Resetting MMCM and RFDC separately will become a requirement once we
start to also program the MMCM. As of now, it is merely a refactoring,
and we continue to use default MMCM settings.
- Adds startup_tiles() and shutdown_tiles()
- The latter is called on tear_down() to be compliant with Xilinx'
documentation on bitstream reconfiguration
This is a debugging utility for MPM, where gdb-based debugging sometimes
leads to issues with timing. To use it, replace class instantiations
such as:
```python
c = SomeClass(arg1, arg2)
```
with
```python
c = LogWrapper(
parent_log.getChild("SomeClass"), "info", SomeClass(arg1, arg2))
```
The class can be used as before, but the MPM log will include calls with
arguments, return values, and execution times, like this:
```
[MPM.PeriphManager.rfdcctl] [INFO] set_if(1, 0, True, 1058240000.0)
[MPM.PeriphManager.rfdcctl] [INFO] --> True [Execution time: 0.108 ms]
```
This change adds a flag to the clock policy that tells the sample PLL to
enable or disable the PLL ref clock (PRC) that goes to the
daughterboards. While for X410 the PRC is required, future USRPs may not
want the clock signal to propagate to the board.
This by itself does not enable dual-rate (or multi-mcr), but it
refactors the code to enable it in the future. Additional changes may be
required.
X4xxClockMgr is renamed to X4xxClockManager.
This changes the behaviour of the examples in a way that leaving
out the --ref argument will not force it to be 'internal'. Previously,
the following command:
rx_samples_to_file --args type=xxx,clock_source=external
would still use the internal reference, because the default value for
--ref was internal, and no other value for --ref was provided. Even
worse, the following command:
rx_samples_to_file --args \
type=xxx,clock_source=external,time_source=external
might throw errors/warnings, because internal clock source plus external
time source is generally not supported, and the example would force the
clock source to be internal unless `--ref internal` was also provided.
For all cases that `clock_source` or `time_source` were not given as
a device argument, this is a no-op because `internal` is the default
value anyway.
In two examples, this includes minor code changes:
- In rfnoc_radio_loopback, if both --ref and --pps were given, we now
use set_sync_source() to speed up setting the reference sources. On
the N310/N300 series in particular, this saves a few seconds at
initialization over the previous implementation (which set clock and
time reference separately).
- In test_dboard_coercion, the code would fail without a default value
for --ref, so we no longer require such a default value.
Before this change, x4xx_rfdc_ctrl.py had various backdoors to read out
required settings. Now that we have the clock policy object, we can
simply read them out from there.
This obviates some code paths (get_rfdc_resampling_factor(),
get_default_mcr(), set_rfdc_reset_cb()).
On tear_down() (this is most commonly seen by users when updating the
FPGA image), we add a check to verify that subcomponents of the X4xx are
actually initialized, to avoid displaying a non-fatal error message that
looks like this:
[ERROR] [MPM.RPCServer] Error in update_component while resetting:
'NoneType' object has no attribute 'tear_down'
The most common/easy way to trigger this error is by loading MPM with
a bitfile that has an invalid compat number (which would stop MPM from
initializing the RFDC controls) and then running `uhd_image_loader`
(which would force a tear_down()). In that circumstance, MPM would try
to call tear_down() on an uninitialized object.
