mpm: x4xx: Separate RFDC clock and tile reset

This adds X4xxRfdcCtrl.reset_tiles(), which resets all enabled tiles and
sets their registers and settings back to initial defaults. The same
functionality was previously implemented in reset_rfdc(), but we want to
be able to reset the RFDC clocks without clearing all registers.

During device initialization, however, we retain this reset of all tiles
by modifying the initialization sequence.

mpm/python/usrp_mpm/periph_manager/x4xx_clock_mgr.py

@@ -257,7 +257,14 @@ class X4xxClockManager:
         self.rfdc = rfdc
         # Update the policy with new info on the FPGA image:
         self.clk_policy.set_dsp_info(self.rfdc.get_dsp_info())
-
+        # Force reset the RFDC to ensure it is in a good state. Note that for
+        # pulling the RFDC out of reset, we need access to the rfdc object, and
+        # the clocking policy needs access to the DSP info, meaning this is the
+        # earliest point during initialization when we can do this reset.
+        self._reset_clocks(True, ('mmcm', 'rfdc'))
+        self._reset_clocks(False, ('mmcm', 'rfdc'))
+        # Also restart the ADC/DAC tiles. This will nuke any previous settings.
+        self.rfdc.reset_tiles()
         # Now do the full MCR init for the first time. When this is done, all
         # the clocks will be ticking. Now, the policy should know about the
         # FPGA capabilities, and can choose the correct default MCR.
@@ -269,18 +276,6 @@ class X4xxClockManager:
             self.log.warning(
                 f"Requested initial master clock rate {initial_mcr/1e6} MHz is invalid!")
             initial_mcr = self.clk_policy.get_default_mcr()
-        self._master_clock_rates = initial_mcr
-
-        # Force reset the RFDC to ensure it is in a good state. Note that for
-        # pulling the RFDC out of reset, we need access to the rfdc object, and
-        # the clocking policy needs access to the DSP info, meaning this is the
-        # earliest point during initialization when we can do this reset.
-        self._reset_clocks(True, ('mmcm', 'rfdc'))
-        self._reset_clocks(False, ('mmcm', 'rfdc'))
-
-        # The initial default mcr only works if we have an FPGA with
-        # a decimation of 2. But we need the overlay applied before we
-        # can detect decimation, and that requires clocks to be initialized.
         self.set_master_clock_rate([initial_mcr[0],])
 
     @no_rpc

mpm/python/usrp_mpm/periph_manager/x4xx_rfdc_ctrl.py

@@ -308,9 +308,13 @@ class X4xxRfdcCtrl:
         self._rfdc_regs.set_reset_adc_dac_chains(reset=reset)
         if reset:
             self._rfdc_regs.log_status()
-            return
 
-        # Restart tiles in XRFdc
+    @no_rpc
+    def reset_tiles(self):
+        """
+        This resets all ADC/DAC tiles.  All existing register settings are
+        cleared and are replaced with the settings initially configured.
+        """
         # All ADC Tiles
         if not self._rfdc_ctrl.reset_tile(-1, False):
             self.log.warning('Error starting up ADC tiles')
@@ -318,13 +322,12 @@ class X4xxRfdcCtrl:
         if not self._rfdc_ctrl.reset_tile(-1, True):
             self.log.warning('Error starting up DAC tiles')
 
-
     @no_rpc
     def startup_tiles(self):
         """
-        PG269: This API function restarts the tile as requested through Tile_Id. If -1 is passed
-        as Tile_Id, the function restarts all the enabled tiles. Existing register settings are
-        not lost or altered in the process.
+        Restarts all enabled ADC/DAC tiles.
+
+        PG269: Existing register settings are not lost or altered in the process.
         """
         # Startup all ADC Tiles
         if not self._rfdc_ctrl.startup_tile(-1, False):
@@ -336,9 +339,9 @@ class X4xxRfdcCtrl:
     @no_rpc
     def shutdown_tiles(self):
         """
-        PG269: This API function stops the tile as requested through Tile_Id. If -1 is passed as
-        Tile_Id, the function stops all the enabled tiles. The existing register settings are not
-        cleared.
+        Stops all enabled ADC/DAC tiles.
+
+        PG269: The existing register settings are not cleared.
         """
         # Shutdown all ADC Tiles
         if not self._rfdc_ctrl.shutdown_tile(-1, False):