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mpm: x4xx: Make sysref_delay part of clock policy

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This commit is contained in:
Javier Valenzuela 2023-05-22 11:47:38 +02:00 committed by michael-west
parent 6ea98bc6e2
commit a80f8a8250
2 changed files with 25 additions and 8 deletions
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4
mpm/python/usrp_mpm/periph_manager/x4xx_clock_policy.py
View File

@ -55,6 +55,7 @@ class SpllConfig:
prc_divider: int
vcxo_freq: Spll1Vco
sysref_div: int
sysref_delay: int
clkin0_r_div: int
pll1_n_div: int
pll2_prescaler: int
@ -277,6 +278,7 @@ class X410ClockPolicy(X4xxClockPolicy):
'prc_divider': 0x3C if legacy_mode else 0x30,
'vcxo_freq': Spll1Vco.VCO122_88MHz,
'sysref_div': 1152,
'sysref_delay': 32,
'clkin0_r_div': int(ref_clock_freq / pfd1),
'pll1_n_div': 64,
'pll2_prescaler': 2,
@ -291,6 +293,7 @@ class X410ClockPolicy(X4xxClockPolicy):
'prc_divider': 0x3C if legacy_mode else 0x30,
'vcxo_freq': Spll1Vco.VCO100MHz,
'sysref_div': 1200,
'sysref_delay': 32,
'clkin0_r_div': int(ref_clock_freq / pfd1),
'pll1_n_div': 50,
'pll2_prescaler': 3,
@ -305,6 +308,7 @@ class X410ClockPolicy(X4xxClockPolicy):
'prc_divider': 0x3C if legacy_mode else 0x30,
'vcxo_freq': Spll1Vco.VCO122_88MHz,
'sysref_div': 1200,
'sysref_delay': 32,
'clkin0_r_div': int(ref_clock_freq / pfd1),
'pll1_n_div': 64,
'pll2_prescaler': 5,

29
mpm/python/usrp_mpm/periph_manager/x4xx_sample_pll.py
View File

@ -20,16 +20,29 @@ class LMK04832X4xx(LMK04832):
"""
X4xx-specific subclass of the Sample Clock PLL LMK04832 controls.
"""
# Sysref depening on the PLL1 VCO freq
SYSREFFREQ = {100e6: 2.5e6, 122.88e6: 2.56e6}
# PLL1 N Divider depending on the PLL1 VCO freq
PLL1NDIV = {100e6: 50, 122.88e6: 64}
# PLL1 Phase Detector Frequency depending on PLL1 VCO freq
PDF = {100e6: 50e3, 122.88e6: 40e3}
# maximum: 1,1023, but limited as greater dividers generate too low Fin for RFDC anyway
LMK_OUT_DIVIDERS = range(1, 35)
PRC_OUT_DIVIDERS = range(1, 1023)
# Obtainable SYSREF frequencies for each VCXO frequency
SYSREF_CONFIG = { 100e6: ( { 'SYSREF_FREQ': 2.5e6,
'PDF' : 50e3, } ,
{ 'SYSREF_FREQ': 1.25e6,
'PDF' : 50e3, } ,
{ 'SYSREF_FREQ': 0.625e6,
'PDF' : 25e3, } ,
{ 'SYSREF_FREQ': 0.5e6,
'PDF' : 50e3, } ,
),
122.88e6:({ 'SYSREF_FREQ': 2.56e6,
'PDF' : 40e3, } ,
{ 'SYSREF_FREQ': 1.28e6,
'PDF' : 40e3, } ,
{ 'SYSREF_FREQ': 0.64e6,
'PDF' : 40e3, } ,
) ,
}
def __init__(self, pll_regs_iface, log=None):
LMK04832.__init__(self, pll_regs_iface, log)
self._output_freq = None
@ -205,8 +218,8 @@ class LMK04832X4xx(LMK04832):
(0x0139, 0x00), # Set SysRef source to 'Normal SYNC' as we initially use the sync signal to synchronize dividers
(0x013A, (cfg.sysref_div & 0x1F00) >> 8), # SYSREF Divide [12:8]
(0x013B, (cfg.sysref_div & 0x00FF) >> 0), # SYSREF Divide [7:0]
(0x013C, 0x00), # set sysref delay value
(0x013D, 0x20), # shift SYSREF with respect to falling edge of data clock
(0x013C, (cfg.sysref_delay & 0x1F00) >> 8), # SYSREF DDLY [12:8]
(0x013D, (cfg.sysref_delay & 0x00FF) >> 0), # shift SYSREF with respect to falling edge of data clock
(0x013E, 0x03), # set number of SYSREF pulse to 8(Default)
(0x013F, 0x0F), # PLL1_NCLK_MUX = Feedback mux, FB_MUX = External, FB_MUX_EN = enabled
(0x0140, 0x00), # All power down controls set to false.