Niels Garibaldi 17c0114771 fpga: dsp: fix race condition in axi_tag_time_ms ... Fixed an issue when multiple timed DDS commands were present, where the first one was popped and then the second command immediately got popped as well to the stale a lookahead signal. The fix is to clear the lookahead signal and threshold signal on every fifo pop command.		2026-08-28 14:59:35 +01:00
..
blocks	fpga: duc: only include TS in first packet of burst	2026-08-11 10:47:57 +02:00
core	fpga: lib: rfnoc: Merge payload and async FIFO	2026-08-20 17:31:01 +02:00
crossbar	fpga: rfnoc: remove critical path from destination cache	2026-07-11 11:12:17 +02:00
fosphor	rfnoc: Add RFNoC fosphor block	2020-04-14 16:37:43 -05:00
sim	fpga: Ensure constant initial phase of dds phase accumulator	2026-08-10 23:12:25 +02:00
transport_adapters	fpga: x4xx: add registers for activity monitoring to ease timing closure	2025-06-27 17:25:26 -05:00
utils	fpga: lib: add SV wrapper for ctrlport_timer	2026-08-04 10:40:34 +02:00
xport	fpga: lib: add scalability to pcie host datapath components	2026-08-04 10:40:40 +02:00
xport_sv	fpga: removing deprecated FIFO IP cores	2026-08-20 01:46:19 +02:00
.gitignore	fpga: rfnoc: Remove deprecated files	2020-08-23 13:52:26 -05:00
addsub.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
addsub.vhd	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
axi_async_stream.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
axi_bit_reduce.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
axi_clip_complex.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
axi_clip_unsigned.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
axi_clip.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
axi_deserializer.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
axi_drop_partial_packet.v	fpga: rfnoc: fix critical paths in DDC hierarchy	2025-07-15 10:20:32 +02:00
axi_fir_filter_dec.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
axi_fir_filter.v	fpga: rfnoc: reverse FIR filter coefficients to get embedded in DSPE48	2024-04-26 15:19:23 -05:00
axi_join.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
axi_packer.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
axi_pipe_join.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
axi_pipe_mac.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
axi_pipe.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
axi_rate_change_ms_pkg.sv	fpga: dsp: add wideband ddc and duc rfnoc blocks	2026-08-05 08:43:42 +02:00
axi_rate_change_ms.sv	fpga: rfnoc: add TS-on-first-only option to axi_rate_change_ms	2026-08-11 10:47:57 +02:00
axi_rate_change.v	fpga: rfnoc: fix critical paths in DDC hierarchy	2025-07-15 10:20:32 +02:00
axi_repeat.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
axi_round_and_clip_complex.v	fpga: lib: fix missing ports in AXI round and clip complex module	2025-09-29 22:52:22 -05:00
axi_round_and_clip.v	fpga: lib: refactor round and clip to save resources	2025-06-27 17:21:36 -05:00
axi_round_complex.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
axi_round.v	fpga: lib: refactor round and clip to save resources	2025-06-27 17:21:36 -05:00
axi_serializer.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
axi_sync.v	fpga: lib: Clean up and document lib files	2021-08-08 14:59:26 -05:00
axi_tag_time_ms_pkg.sv	fpga: dsp: add wideband ddc and duc rfnoc blocks	2026-08-05 08:43:42 +02:00
axi_tag_time_ms.sv	fpga: dsp: fix race condition in axi_tag_time_ms	2026-08-28 14:59:35 +01:00
axi_tag_time.v	fpga: rfnoc: fix critical path in DUC hierarchy	2025-07-15 10:20:32 +02:00
cadd.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
cic_decimate.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
cic_interpolate.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
complex_invert.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
complex_to_mag_approx.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
complex_to_magsq.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
conj.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
const_sreg.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
const.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
counter.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
cvita_hdr_decoder.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
cvita_hdr_encoder.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
cvita_hdr_modify.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
cvita_hdr_parser.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
data_types.vh	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
datapath_gatekeeper.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
ddc_ms_regs_pkg.sv	fpga: dsp: add wideband ddc and duc rfnoc blocks	2026-08-05 08:43:42 +02:00
ddc_ms.sv	fpga: dsp: add wideband ddc and duc rfnoc blocks	2026-08-05 08:43:42 +02:00
ddc.v	fpga: rfnoc: ddc: fix strobe_dds_clip assignment	2025-08-19 17:55:08 +02:00
dds_freq_tune_duc.v	fpga: lib: Fix Vivado warnings	2023-06-09 09:01:04 -05:00
dds_freq_tune.v	FPGA: Fix warnings in dds_freq_tune module	2023-01-19 10:05:27 -06:00
dds_ms.sv	fpga: Ensure constant initial phase of dds phase accumulator	2026-08-10 23:12:25 +02:00
dds_timed.v	fpga: rfnoc: Fix EOB loss in DUC	2021-08-08 14:59:26 -05:00
dds_wrapper.v	fpga: rfnoc: Fix EOB loss in DUC	2021-08-08 14:59:26 -05:00
delay_fifo.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
delay_type2.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
delay_type3.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
delay_type4.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
duc_ms_regs_pkg.sv	fpga: dsp: add wideband ddc and duc rfnoc blocks	2026-08-05 08:43:42 +02:00
duc_ms.sv	fpga: dsp: add wideband ddc and duc rfnoc blocks	2026-08-05 08:43:42 +02:00
duc.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
fft_shift.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
file_sink.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
file_source.v	fpga: Fix errors found by linting with vsim	2020-03-23 08:23:51 -05:00
fir_filter_slice.v	fpga: rfnoc: reverse FIR filter coefficients to get embedded in DSPE48	2024-04-26 15:19:23 -05:00
join_complex.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
keep_one_in_n.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
Makefile.srcs	fpga: dsp: add wideband ddc and duc rfnoc blocks	2026-08-05 08:43:42 +02:00
moving_sum.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
mult_add_rc.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
mult_add.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
mult_rc.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
mult.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
multiply.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
noc_traffic_counter.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
null_source.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
periodic_framer.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
phase_accum.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
ram_to_fifo.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
sine_tone.v	siggen: Fix direction of rotation	2021-10-27 07:56:09 -07:00
split_complex.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
split_stream_fifo.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
split_stream.v	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00
vector_iir.v	fpga: rfnoc: Add Vector IIR RFNoC block	2020-05-19 14:22:55 -05:00