Marian Koop 8d9c53c83e ci: fpga: Added pipeline switch to optionally build alternate X420 designs ... Added pipeline switch to select between building X420_CG targets with (default) or w/o DDC/DUC (alternate). In the pipeline the default is to build the alternative design because of the low compile success rates for these fpga designs when DDC/DUC is included.		2026-08-23 02:02:27 +02:00
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docker	ci: Add Python 3.13 support	2026-08-20 02:03:09 +02:00
fpga	fpga: ci: use latest version of hwtools	2026-08-20 13:27:17 +02:00
hwtools	fpga: lib: move ctrlport_to_jtag to lib sirectory	2026-08-14 16:32:09 -05:00
templates	ci: fpga: Added pipeline switch to optionally build alternate X420 designs	2026-08-23 02:02:27 +02:00
utils	ci: docker: Enable support for partial docker pipelines	2026-08-10 09:51:18 +02:00
uhd-build-docker-container.yml	ci: docker: Re-add python 3.13 targets	2026-08-20 02:03:09 +02:00
uhd-hardware-test-dev.yml	ci: add ddc/duc ats template tests for x410_x4_400	2026-08-20 17:08:19 +02:00
uhd-hardware-test-weekly-pipeline.yml	ci: add ddc/duc ats template tests for x410_x4_400	2026-08-20 17:08:19 +02:00
uhd-pipeline-pr.yml	ci: fpga: Added pipeline switch to optionally build alternate X420 designs	2026-08-23 02:02:27 +02:00
uhd-pipeline-vars.yml	ci: select docker image repo directly at container endpoint definitions	2023-07-28 15:13:44 -05:00
uhd-pipeline.yml	ci: fpga: Added pipeline switch to optionally build alternate X420 designs	2026-08-23 02:02:27 +02:00