ci: fpga: Added pipeline switch to optionally build alternate X420 designs

Added pipeline switch to select between building X420_CG targets
with (default) or w/o DDC/DUC (alternate). In the pipeline the default
is to build the alternative design because of the low compile success
rates for these fpga designs when DDC/DUC is included.

.ci/templates/stages-uhd-pipeline.yml

@@ -252,6 +252,10 @@ parameters:
       timeout: 720
       attempt_timeout: 360
       max_attempts: 2
+- name: use_low_success_fpga_targets
+  type: boolean
+  displayName: Force use of FPGA with low-success compile rates
+  default: true
 # Next parameters are used to control conditional execution of embedded system image build stages.
 # They are not parameters that can be set by the user,
 # but rather they are computed based on the output of the analyze_changeset stage.
@@ -777,7 +781,28 @@ stages:
     package_access: ${{ parameters.package_access }}
     fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
     x410_targets_matrix: ${{ parameters.x410_targets_matrix }}
-    x420_targets_matrix: ${{ parameters.x420_targets_matrix }}
+    x420_targets_matrix:
+      ${{ if eq(parameters.use_low_success_fpga_targets, false) }}:
+        # Keep all X420 targets except X420_CG_1000 and X420_CG_400
+        ${{ each pair in parameters.x420_targets_matrix }}:
+          ${{ if and(ne(pair.key, 'X420_CG_1000'), ne(pair.key, 'X420_CG_400')) }}:
+            ${{ pair.key }}: ${{ pair.value }}
+        # Re-add targets with overrides
+        X420_CG_1000:
+          ${{ each pair in parameters.x420_targets_matrix.X420_CG_1000 }}:
+            ${{ if ne(pair.key, 'image_core') }}:
+              ${{ pair.key }}: ${{ pair.value }}
+            ${{ else }}:
+              image_core: x420_CG_1000_woDDC_rfnoc_image_core.yml
+        X420_CG_400:
+          ${{ each pair in parameters.x420_targets_matrix.X420_CG_400 }}:
+            ${{ if ne(pair.key, 'image_core') }}:
+              ${{ pair.key }}: ${{ pair.value }}
+            ${{ else }}:
+              image_core: x420_CG_400_woDDC_rfnoc_image_core.yml
+      ${{ else }}:
+        ${{ each pair in parameters.x420_targets_matrix }}:
+          ${{ pair.key }}: ${{ pair.value }}
     x440_targets_matrix: ${{ parameters.x440_targets_matrix }}
     additional_setup_steps:
       - checkout: rfnoc-oot-blocks

.ci/uhd-pipeline-pr.yml

@@ -135,6 +135,10 @@ parameters:
   - 'files.ettus.com (Public)'
   displayName: Published Package Access
   default: 'Internal'
+- name: use_low_success_fpga_targets
+  type: boolean
+  displayName: Force use of FPGA with low-success compile rates
+  default: false
 - name: selected_streaming_tests
   type: string
   displayName: Streaming Tests Multi-Select (comma-separated)
@@ -185,5 +189,8 @@ extends:
     publish_int_files: true
     package_and_publish_images: ${{ parameters.package_and_publish_images }}
     package_access: ${{ parameters.package_access }}
+    use_low_success_fpga_targets: ${{ parameters.use_low_success_fpga_targets }}
+    # Test parameters
     selected_streaming_tests: ${{ parameters.selected_streaming_tests }}
+    
     

.ci/uhd-pipeline.yml

@@ -118,6 +118,10 @@ parameters:
   - 'files.ettus.com (Public)'
   displayName: Published Package Access
   default: 'Internal'
+- name: use_low_success_fpga_targets
+  type: boolean
+  displayName: Force use of FPGA with low-success compile rates
+  default: false
 - name: selected_streaming_tests
   type: string
   displayName: Streaming Tests Multi-Select (comma-separated)
@@ -165,4 +169,6 @@ extends:
     publish_int_files: true
     package_and_publish_images: ${{ parameters.package_and_publish_images }}
     package_access: ${{ parameters.package_access }}
+    use_low_success_fpga_targets: ${{ parameters.use_low_success_fpga_targets }}
+    # Test parameters
     selected_streaming_tests: ${{ parameters.selected_streaming_tests }}