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ci: add ddc/duc ats template tests for x410_x4_400
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@ -932,6 +932,7 @@ stages:
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fpga_imgs_source: 'Pipeline'
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${{ else }}:
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fpga_imgs_source: 'Filesystem'
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runX410X4400RfSubset: true
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testLength: ${{ parameters.testLength }}
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- template: tests/job-uhd-x440-hardware-tests-pebbles.yml
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parameters:
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@ -13,6 +13,9 @@ parameters:
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- name: extra_rf_test_args
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type: string
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default: ''
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- name: runX410X4400RfSubset
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type: boolean
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default: false
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- name: testLength
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type: string
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@ -25,6 +28,7 @@ jobs:
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runPyTestNonRF: false
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runDevTest: false
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runSystemImageTest: false
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runX410X4400RfSubset: ${{ and(parameters.runX410X4400RfSubset, eq(parameters.fpga_imgs_source, 'Pipeline')) }}
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uhdArtifactSource: ${{ parameters.uhdArtifactSource }}
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uhdFpgaArtifactSource: ${{ parameters.uhdFpgaArtifactSource }}
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fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
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@ -40,5 +44,6 @@ jobs:
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uartSerial: $(x410_uartSerial)
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pipelineAgent: pebbles-agent-1
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pytestAtsConfig: uhd_oss_ats
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pytestConfigDut: 'x410-400'
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pytestDUT: 'x410'
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sfp0ip: '192.168.30.62'
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@ -18,6 +18,9 @@ parameters:
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- name: runRfnocBlockTest
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type: boolean
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default: false
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- name: runX410X4400RfSubset
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type: boolean
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default: false
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- name: forceIQCorrections
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type: boolean
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default: false
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@ -422,6 +425,37 @@ jobs:
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resultFileNameBase: 'complex_gain_block_test'
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testSelector: 'test_radio_control_complex_gain.py'
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- ${{ if parameters.runX410X4400RfSubset }}:
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- template: ../../steps-download-fpga-artifact.yml
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parameters:
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dutType: $(pytestDUT)
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dutFPGA: 'X4_400'
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fpgaArtifactSource: ${{ parameters.uhdFpgaArtifactSource }}
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fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
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- script: |
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UHD_INSTALL_PATH=$(uhd_artifact_directory)/uhddev-$(testOS)-${{ parameters.toolset }}/uhddev/build-installed
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export PATH=$UHD_INSTALL_PATH/bin:$PATH
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if [ -d "$UHD_INSTALL_PATH/lib64" ]; then
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export LD_LIBRARY_PATH=$UHD_INSTALL_PATH/lib64:$LD_LIBRARY_PATH
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else
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export LD_LIBRARY_PATH=$UHD_INSTALL_PATH/lib:$LD_LIBRARY_PATH
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fi
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uhd_image_loader --args type=$(dutType),addr=$(USRP_EMB_TARGET_IP) \
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--fpga=$FPGA_ARTIFACT_DIR/$FPGA_BITFILE_NAME.bit
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displayName: 'X410/X4_400 RF subset: Load FPGA on USRP'
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- template: step-uhd-run-pytest-on-host.yml
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parameters:
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runPyTest: true
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displayString: 'X410/X4_400 RF subset'
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testFolder: 'pytests'
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pytestConfigDut: $(pytestConfigDut)
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testSelector: 'test_ddc_response.py test_rx_offset_tone_sweep.py test_tx_offset_tone_sweep.py'
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testLength: ${{ parameters.testLength }}
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warmUpAfterBoot: ${{ parameters.warmUpAfterBoot }}
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toolset: ${{ parameters.toolset }}
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# Run the mender tests last because they
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# modify the flashed image on the device
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- script: |
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@ -10,6 +10,12 @@ parameters:
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- name: extra_rf_test_args
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type: string
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default: ''
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- name: pytestConfigDut
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type: string
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default: '$(pytestDUT)'
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- name: testSelector
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type: string
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default: '.'
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- name: testLength
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type: string
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default: 'smoke'
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@ -69,7 +75,7 @@ steps:
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source $(Build.SourcesDirectory)/ettus-rts/config/remote/python_tests/setup_venv.sh
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cd $(Build.SourcesDirectory)/ettus-rts/config/remote/python_tests/${{ parameters.testFolder }}
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python3 ../automated_main.py --test_selector . --ats_config $(pytestAtsConfig) --dut $(pytestDUT) --run_vars_overrides 'mgmt_addr=$(USRP_EMB_TARGET_IP)' --results_path '$(Common.TestResultsDirectory)/pytest/host' --test_length ${{ parameters.testLength }} ${{ parameters.extra_rf_test_args }}
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python3 ../automated_main.py --test_selector ${{ parameters.testSelector }} --ats_config $(pytestAtsConfig) --dut ${{ parameters.pytestConfigDut }} --run_vars_overrides 'mgmt_addr=$(USRP_EMB_TARGET_IP)' --results_path '$(Common.TestResultsDirectory)/pytest/host' --test_length ${{ parameters.testLength }} ${{ parameters.extra_rf_test_args }}
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displayName: Run ${{ parameters.displayString }} on host
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continueOnError: true
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condition: and(succeeded(), ${{ parameters.runPyTest }})
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@ -325,6 +325,7 @@ stages:
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uhdArtifactSource: uhd_mono_pipeline
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uhdFpgaArtifactSource: ${{ variables.uhdFpgaArtifactSource }}
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fpga_imgs_source: ${{ variables.fpga_imgs_source }}
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runX410X4400RfSubset: true
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extra_rf_test_args: ${{ parameters.extra_rf_test_args }}
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testLength: ${{ parameters.testLength }}
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@ -126,6 +126,7 @@ stages:
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uhdArtifactSource: uhd_mono_pipeline
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uhdFpgaArtifactSource: ${{ variables.uhdFpgaArtifactSource }}
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fpga_imgs_source: ${{ variables.fpga_imgs_source }}
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runX410X4400RfSubset: true
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testLength: ${{ parameters.testLength }}
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- template: templates/tests/job-uhd-x440-hardware-tests-pebbles.yml
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parameters:
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