Replacing the synth target of the FPGA Makefiles with the normal "bin" flow
which ends after synthesis if desired. This aligns the build flows in case ILAs
want to be added.
Some testbenches were overwriting DESIGN_SRCS, but this gets
initialized in viv_sim_preamble.mak and overwriting it causes some
necessary files to be removed from the file list.
This adds support for block write, block read, and poll operations in
the AXIS-Ctrl endpoint.
A burst mode is also now supported, in which the READ or WRITE opcode
with NumData > 1 allows repeated reads or writes to the same address,
unlike block write/read, which auto-increments the address.
This change also removes the requirement for dummy data words to be
present in read request packets as well as write and sleep response
packets. This improves efficiency of the control interface, especially
for block and burst operations.
Main changes are:
- Creating Xilinx FIR filters based on the X410 ones
- Writing TX and RX resamplers with seperate testbenches
- Creating a RF core around the resamplers and rf_core_full for the 200M variant
specifically.
- Integration of the core into the FPGA top level based on conditional
parameters generated by the rfnoc_image_builder workflow
- Changing the 8 SPC to 2 SPC to save DSP resources for the 200M image only
- Adding reset handling from ps_rfdc_bd to the new rf_core.
This fixes special build targets (rtl, synth) that pull in RFNoC blocks
which use RFNOC_OOT_SRCS. Since fa7c3604, we create an OOT source file
to avoid ARG_MAX issues, but these special targets were not updated to
respect this. This would be a problem when using the --SYNTH or --CHECK
flags on a clean build from rfnoc_image_builder.
This adds support for the new USRP X420. It is the latest addition to
our X4xx series and comes with two HBX daughterboards. The HBX is
a one-channel direct conversion transceiver that covers 5G NR FR3 and
X-/KU-Band needs for Research and Prototyping in a frequency range of 10
MHz up to 20 GHz. It supports analog bandwidths of up to 1 GHz.
This commit is the FPGA portion of the X420 support.
Co-authored-by: Markus Schill <markus.schill@emerson.com>
For enabling subchannels within logical channels, the RFDC memory needs
to hold the information about what the subchannels are (e.g. Real, I or
Q). This commit adds this and removes the reordering of channels on the
TX side for X440's ADC self-cal. This is a breaking change, therefore
the FPGA compat number gets bumped, too.
Use a resources file to pass RFNoC OOT source files to Vivado TCL
scripts, avoiding ARG_MAX argument list limits.
Co-authored-by: Martin Braun <martin.braun@ettus.com>
