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fpga: x4xx: fix typo in DIO pin mapping description

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Max Köhler 2026-01-13 16:11:40 +01:00 committed by Martin Braun
parent 4ac5706b1f
commit 56f5002b1a
4 changed files with 6 additions and 6 deletions
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4
fpga/usrp3/top/x400/doc/X410/X410_FPGA.htm
View File

@ -8938,7 +8938,7 @@ Set of configuration registers for the supported slaves.
+--------------------------------------+</pre>
</li>
<li>
Up until FPGA compat number 10.0, the the bit order did not match the
Up until FPGA compat number 10.0, the bit order did not match the
actual pin order on the frontpanel connectors. To compensate for this,
the software had to apply a mapping table for the values in bitfield
DIO_PORT_A (see parameter 'MAPPED_PIN_DIO_A' in x4xx.sv) and another
@ -15813,7 +15813,7 @@ attenuation setting desired. Writing zero to this field results in no attenuatio
(HEC/ARC) left out).
</li>
<li>
Up until FPGA compat number 10.0, the the bit order did not match the
Up until FPGA compat number 10.0, the bit order did not match the
actual pin order on the frontpanel connectors. To compensate for this,
the software had to apply a mapping table for the values in bitfield
DIO_PORT_A (see parameter 'MAPPED_PIN_DIO_A' in x4xx.sv) and another

4
fpga/usrp3/top/x400/doc/X440/X440_FPGA.htm
View File

@ -5949,7 +5949,7 @@ Set of configuration registers for the supported slaves.
+--------------------------------------+</pre>
</li>
<li>
Up until FPGA compat number 10.0, the the bit order did not match the
Up until FPGA compat number 10.0, the bit order did not match the
actual pin order on the frontpanel connectors. To compensate for this,
the software had to apply a mapping table for the values in bitfield
DIO_PORT_A (see parameter 'MAPPED_PIN_DIO_A' in x4xx.sv) and another
@ -10577,7 +10577,7 @@ Controls which source is forwarded to the <a href="#DIO_REGMAP|DIO_MASTER_REGIST
(HEC/ARC) left out).
</li>
<li>
Up until FPGA compat number 10.0, the the bit order did not match the
Up until FPGA compat number 10.0, the bit order did not match the
actual pin order on the frontpanel connectors. To compensate for this,
the software had to apply a mapping table for the values in bitfield
DIO_PORT_A (see parameter 'MAPPED_PIN_DIO_A' in x4xx.sv) and another

2
fpga/usrp3/top/x400/x4xx_dio.v
View File

@ -485,7 +485,7 @@ endmodule
// +--------------------------------------+</pre>
// </li>
// <li>
// Up until FPGA compat number 10.0, the the bit order did not match the
// Up until FPGA compat number 10.0, the bit order did not match the
// actual pin order on the frontpanel connectors. To compensate for this,
// the software had to apply a mapping table for the values in bitfield
// DIO_PORT_A (see parameter 'MAPPED_PIN_DIO_A' in x4xx.sv) and another

2
fpga/usrp3/top/x400/x4xx_gpio_atr.v
View File

@ -300,7 +300,7 @@ endmodule
// (HEC/ARC) left out).
// </li>
// <li>
// Up until FPGA compat number 10.0, the the bit order did not match the
// Up until FPGA compat number 10.0, the bit order did not match the
// actual pin order on the frontpanel connectors. To compensate for this,
// the software had to apply a mapping table for the values in bitfield
// DIO_PORT_A (see parameter 'MAPPED_PIN_DIO_A' in x4xx.sv) and another