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b4aeb78438
Added variants for the DDC/DUC blocks that can process multiple samples per cycle and can be used for bandwidths higher than 200Mhz. This new feature is integrated into the existing RFNoC DDC/DUC blocks. Depending on the Radio bandwidth specified for the USRP variant, the DxC blocks will instantiate the existing singlesample implementation(for FPGA image variants <= 200MHz) or instantiate the multisample implementation(for FPGA image variants > 200MHz). Co-authored-by: Niels Garibaldi <niels.steffen.garibaldi@emerson.com> Co-authored-by: André Zoch <andre.zoch@emerson.com> Co-authored-by: Meghana Halladamath <meghana.halladamath@emerson.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Max Köhler <max.koehler@emerson.com> |
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| .. | ||
| test/ChdrIfaceBfm | ||
| ctrlport_bfm_pkg.sv | ||
| Makefile.srcs | ||
| PkgAxiLiteBfm.sv | ||
| PkgAxisCtrlBfm.sv | ||
| PkgAxiStreamBfm.sv | ||
| PkgChdrBfm.sv | ||
| PkgChdrData.sv | ||
| PkgChdrIfaceBfm.sv | ||
| PkgChdrUtils.sv | ||
| PkgCtrlIfaceBfm.sv | ||
| PkgEthernet.sv | ||
| PkgRfnocBlockCtrlBfm.sv | ||
| PkgRfnocItemUtils.sv | ||
| PkgTestExec.sv | ||
| sim_clock_gen.sv | ||
| test_exec.svh | ||