fpga: sim: fix ASSERT_INFO macro

2026-10-25 17:36:10 +00:00 · 2025-09-18 23:10:51 +02:00 · 2025-09-18 23:10:51 +02:00 · 1ff8ae94cd
commit 1ff8ae94cd
parent 3c6df18579
1 changed files with 1 additions and 1 deletions
--- a/fpga/usrp3/sim/rfnoc/test_exec.svh
+++ b/fpga/usrp3/sim/rfnoc/test_exec.svh
@ -100,7 +100,7 @@ timeprecision 1ps;
 `define ASSERT_INFO(EXPR, MESSAGE)                                   \
  begin                                                              \
    assert (EXPR) else begin                                         \
-      $info(MESSAGE)                                                 \
+      $info(MESSAGE);                                                \
    end                                                              \
  end