Max Köhler a9ddd67fb9 fpga: lib: rfnoc: Merge payload and async FIFO ... Merge the payload and async FIFOs in the axis_data_to_chdr and chdr_to_axis_data conversion conversion modules.		2026-08-20 17:31:01 +02:00
..
export/x300/radio	fpga: removing deprecated FIFO IP cores	2026-08-20 01:46:19 +02:00
lib	fpga: lib: rfnoc: Merge payload and async FIFO	2026-08-20 17:31:01 +02:00
sim	fpga: dsp: add wideband ddc and duc rfnoc blocks	2026-08-05 08:43:42 +02:00
tools	fpga: lib: enable XPM fifo for all Xilinx FPGAs	2026-08-20 01:46:19 +02:00
top	fpga: n3xx: fix UART initialization for WX image	2026-08-20 01:48:27 +02:00
.gitignore	Move ignore of build folders into top level	2025-07-18 11:19:52 +02:00
build.py	fpga: Replace references to python -> python3	2023-12-05 15:43:08 -06:00
LICENSE.md	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00