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Ryan Volz a57c162a0d fpga/usrp3: Fix DC truncation bias by adding rounding to DDC chain. 
A digital DC bias caused by various truncations in the DDC chain was
previously noticable with small signal levels, especially with high
decimation rates. This patch eliminates the bias by replacing the
truncation with rounding or simply keeping more bits for longer where it
makes sense.

This is essentially a forward port of a similar prior fix to the usrp2
DDC chain: https://github.com/EttusResearch/fpga/pull/4.

Signed-off-by: Ryan Volz <ryan.volz@gmail.com>
2024-06-11 10:20:08 +02:00
..
.ci ci: Update FPGA CI pipelines to match new image builder 2024-06-11 10:20:08 +02:00
docs fpga: Align build process for all targets 2024-06-11 10:20:08 +02:00
usrp1 Merge FPGA repository back into UHD repository 2020-01-28 09:35:36 -08:00
usrp2 fpga: usrp2: update build tools to use python3 2021-12-08 12:08:29 -08:00
usrp3 fpga/usrp3: Fix DC truncation bias by adding rounding to DDC chain. 2024-06-11 10:20:08 +02:00
.clang-format fpga: Clear clang-format settings for FPGA code 2023-08-17 10:51:55 -05:00
.gitignore fpga: Add more spurious files to gitignore 2023-12-13 17:28:09 -06:00
CODING.md fpga: Update recommended HDL header guideline 2021-06-10 11:56:58 -05:00
CONTRIBUTING.md Merge FPGA repository back into UHD repository 2020-01-28 09:35:36 -08:00
README.md Merge FPGA repository back into UHD repository 2020-01-28 09:35:36 -08:00

README.md

Ettus Research USRP FPGA HDL Source

Welcome to the USRP FPGA HDL source code tree! This repository contains free & open-source FPGA HDL for the Universal Software Radio Peripheral (USRP™) SDR platform, created and sold by Ettus Research. A large percentage of the source code is written in Verilog.

Product Generations

This repository contains the FPGA source for the following generations of USRP devices.

Generation 1

  • Directory: usrp1
  • Devices: USRP Classic Only
  • Tools: Quartus from Altera
  • Build Instructions

Generation 2

Generation 3

  • Directory: usrp3
  • Devices: USRP B2X0, USRP X Series, USRP E3X0, USRP N3xx
  • Tools: Vivado from Xilinx, ISE from Xilinx, GNU make
  • Build Instructions
  • Simulation

Pre-built FPGA Images

Pre-built FPGA and Firmware images are not hosted here. Please visit the FPGA and Firmware manual page for instructions on downloading and using pre-built images. In most cases, running the following command will do the right thing.

$ uhd_images_downloader

Building This Manual

This FPGA manual is available on the web at http://files.ettus.com/manual/md_fpga.html for the most recent stable version of UHD. If you wish to read documentation for a custom/unstable branch you will need to build it and open it locally using a web browser. To do so please install Doxygen on your system and run the following commands:

$ cd docs
$ make
$ sensible-browser html/index.html