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1,093 Commits 30 Branches 162 Tags 270 MiB
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Author SHA1 Message Date
Josh Blum
df2c9b3af8 E110: revert Makefile for E110, the UCF was accidentally removed 2013-04-02 18:11:19 -07:00
Josh Blum
81447a405e e110: fixes from last commit 2013-03-18 18:33:11 -07:00
Josh Blum
a370cb47bb e100: switch to fixed length xfers 2013-03-14 17:49:57 -07:00
Josh Blum
8d91709d43 fpga: added logging to makefile common 2013-03-05 22:34:48 -08:00
Josh Blum
58ee775d1f b100: tighten timing, added p2p constraint + ignores 
Bumped u1p compat minor, now its 11.2
 2013-03-05 22:32:38 -08:00
Josh Blum
784edbdf54 b100: install rx data minimum occupancy logic 2012-10-09 17:59:39 -07:00
Josh Blum
60d3f8d448 b100: added final fifo for min occupancy check 2012-10-09 17:49:12 -07:00
Josh Blum
248743ac83 b100: fix syntax error in packet_padder36 2012-10-09 17:02:59 -07:00
Josh Blum
f83847318f b100/e100: bump compat for inversion fix on master 2012-10-05 14:11:42 -07:00
Josh Blum
8cfb73ed7d e1x0: fix RX ADC I and Q inversion 2012-10-05 14:11:01 -07:00
Josh Blum
ac9b1049b5 Merge branch 'maint' 
Conflicts:
	usrp2/top/B100/u1plus_core.v
	usrp2/top/E1x0/E1x0.v
	usrp2/top/E1x0/u1e_core.v
 2012-10-05 14:10:19 -07:00
Josh Blum
1db5653325 b100/e100: bump compat minor for inversion fix 2012-10-05 13:41:22 -07:00
Josh Blum
a631a912af e1x0: fix RX ADC I and Q inversion 2012-10-05 13:41:22 -07:00
Josh Blum
503d95c583 b100: fix RX ADC I and Q inversion 2012-10-05 13:41:22 -07:00
Josh Blum
bf6ced26b4 b100: fpga makefile for 2rx no tx 2012-09-01 23:14:49 -07:00
Josh Blum
a8a02f97a8 e100: tighten timing - less routing on EM_A 
There were a few places it was ok to use addr over EM_A.
This makes routing sligtly easier for GPMC signals.
 2012-07-19 20:35:37 -07:00
Josh Blum
bd807be751 u1plus: added sr misc hook for clock sync 2012-07-18 13:45:42 -07:00
Josh Blum
9ecbfeb8ee e100: renamed top level for E100/E110 to E1x0 
Some minor tweaks to gpmc_to_fifo + timing
 2012-07-17 12:28:29 -07:00
Josh Blum
0ff64ba45e E100: squash E100/E110 top level work 
Implements timed commands and FIFO control.
Uses control and data FIFOs for GPMC.
Uses the common core for E100/B100.
 2012-07-16 20:37:02 -07:00
Josh Blum
3e87c6ba2f gpmc: squashed GPMC FIFO work for E100 
The control and data slaves are now both implemented as FIFOs.
Requires another squash of E100 top level to use.
 2012-07-16 20:36:45 -07:00
Josh Blum
febc5e2a68 gpmc: tighter timing constraints and easier to route gpmc to fifo 2012-07-16 20:33:07 -07:00
Josh Blum
c587f0204a Merge branch 'master' into next 2012-07-16 20:31:57 -07:00
Josh Blum
1b31a8780d Merge branch 'maint' 
Conflicts:
	usrp2/top/E1x0/u1e_core.v
 2012-07-16 18:36:29 -07:00
Josh Blum
38ec062b62 e100: offset gpmc to fifo writes by 2 transfers 
This effectivly works around bus initial transaction issues.
 2012-07-15 22:50:19 -07:00
Josh Blum
90f9cddd68 e100: reverted commit registering in gpmc 
There is a subtle bus issue that the last changset did not address.
 2012-07-15 22:43:52 -07:00
Josh Blum
295c7e7b98 B100: squash B100 top level work 
Implements timed commands and FIFO control.
Uses control and data FIFOs for GPIF.
Implements a common core for E100/B100.
 2012-07-02 12:56:22 -07:00
Josh Blum
c19e10d790 gpif: squashed GPIF slave fifo work for B100 
The control and data enpoints are now both implemented as FIFOs.
Requires another squash of B100 top level to use.
 2012-07-02 12:52:48 -07:00
Josh Blum
028a2bb631 fifo: added module packet_padder36 to fifo/ 2012-07-02 12:38:35 -07:00
Josh Blum
f139c98ae7 b100: removed unused proto files 2012-06-13 22:47:58 -07:00
Josh Blum
6d6eb1e634 fpga: added setting regs based simple_i2c_core 2012-05-30 13:38:20 -07:00
Josh Blum
b269285353 fpga: added some parameterization to settings_fifo_ctrl 2012-05-30 13:37:21 -07:00
Josh Blum
8b8a60558a fpga: added various models from ISE 2012-05-30 13:36:42 -07:00
Josh Blum
3cf4977c02 Merge branch 'maint' 2012-05-22 14:00:59 -07:00
Al Fayez
002f7edd50 Added registers for gpmc-to-fifo interface to address sequence errors for E100/E110 2012-05-22 14:00:33 -07:00
Josh Blum
9786c2bd7b Merge branch 'maint' 
Conflicts:
	usrp2/top/E1x0/u1e_core.v
 2012-05-10 20:33:43 -07:00
Josh Blum
db1d63ecaa e100: bump compat minor for xclock reader fix 2012-05-10 20:31:20 -07:00
Josh Blum
af018ded46 fpga: xclock fix for edge case condition 2012-05-08 13:45:26 -07:00
Josh Blum
cb313ea980 e100/b100: bumped compat number for timed commands merge 
There were common FPGA changes and an incompatibility.
This should have been done before the merge anyhow.
 2012-04-25 17:59:52 -07:00
Nick Foster
70db8e9d1c slave_fifo: use 2KB FIFO size instead of 1KB 2012-04-24 21:57:52 -07:00
Josh Blum
8a00096f98 b100: implement packet-end/flush cycle timeout 2012-04-24 20:02:02 -07:00
Josh Blum
600258c2ab gpif: removed unused gpif related files 2012-04-24 18:00:11 -07:00
Josh Blum
00f515da98 N2x0: updated the bootloader w/ latest from fw 2012-04-20 11:52:21 -07:00
Josh Blum
ed3624aa04 usrp2: remove settings_fifo_ctrl, meets timing 2012-04-20 10:24:01 -07:00
Josh Blum
1ddcad462f fifo ctrl: Nseries timing meets with a single shortfifo 2012-04-17 18:43:25 -07:00
Josh Blum
e8dc93363a usrp: work on meeting timing constraints 
* fifo ctrl register the vita ticks and use late
* vita de/framer make nchans const since we dont change it
* simplify readback muxes to minimal usage
 2012-04-10 19:10:10 -07:00
Josh Blum
510632d896 Merge branch 'master' into next 
Conflicts:
	usrp2/top/N2x0/u2plus_core.v
	usrp2/top/USRP2/u2_core.v
 2012-04-09 19:53:51 -07:00
Josh Blum
bcca51705e Merge branch 'maint' 2012-04-09 19:51:38 -07:00
Josh Blum
f136b06211 vita: moved clear register to overlap with nchan register 
This fixes the bug where setting the format clears the vita RX.
This is only an issue when the noclear option is set by UHD,
because the format register is always so, so it always clears.
Note: noclear is there to support the backwards compat API (pre streamer).

Now, numchans and clear overlap. This is ok because
in the host code, clear and numchans are always used together.

All timing meets on N2xx and USRP2.
 2012-04-09 16:35:31 -07:00
Josh Blum
91f0498372 Merge branch 'maint' 2012-04-02 18:34:06 -07:00
Josh Blum
4c111800a1 b100: fix slave fifo data xfer exit condition 
When exiting the read/write data state,
when the transfer count maxes out/peaks,
the fifo read/write signals were getting this
condition the cycle after with the state change.
 2012-04-01 23:22:39 -07:00