This fixes special build targets (rtl, synth) that pull in RFNoC blocks
which use RFNOC_OOT_SRCS. Since fa7c3604, we create an OOT source file
to avoid ARG_MAX issues, but these special targets were not updated to
respect this. This would be a problem when using the --SYNTH or --CHECK
flags on a clean build from rfnoc_image_builder.
This adds support for the new USRP X420. It is the latest addition to
our X4xx series and comes with two HBX daughterboards. The HBX is
a one-channel direct conversion transceiver that covers 5G NR FR3 and
X-/KU-Band needs for Research and Prototyping in a frequency range of 10
MHz up to 20 GHz. It supports analog bandwidths of up to 1 GHz.
This commit is the FPGA portion of the X420 support.
Co-authored-by: Markus Schill <markus.schill@emerson.com>
For enabling subchannels within logical channels, the RFDC memory needs
to hold the information about what the subchannels are (e.g. Real, I or
Q). This commit adds this and removes the reordering of channels on the
TX side for X440's ADC self-cal. This is a breaking change, therefore
the FPGA compat number gets bumped, too.
Use a resources file to pass RFNoC OOT source files to Vivado TCL
scripts, avoiding ARG_MAX argument list limits.
Co-authored-by: Martin Braun <martin.braun@ettus.com>
This adds an option to not require or wait for the AXIS-Ctrl packet
response for CtrlPort writes. This is useful in cases where the writes
are not critical (e.g., status updates) and occasional packet loss is
expected. Enabling this feature will prevent the endpoint from hanging
in situations where the AXIS-Ctrl write request or the write response
is dropped on the network.
Optimizations aim to reduce number of DSP slices:
For static FIR filter generation (RELOADABLE_COEFFS = 0):
- skip fir_filter_slice instantiation for zero coefficient FIR taps.
Positiion of zero taps derived from COEFFS_VEC.
(cherry pick from Max prototype)
- use fir_filter_slice preadder input to jointly process symmetric
FIR filter taps. Saves almost half the number of fir_filter_slices.
Symmetry automatically inferred from COEFFS_VEC.
TB Changes:
TB has been extended to validate optimizations for zero/symmetric
coefficients depending on the provided filter coefficients.
- axi_fir_multisample_filter_tb.sv: changed interface to pass
FIR filter coefficients from outside.
- axi_fir_multisample_filter_tb_wrapper.sv: splitted into
separate generate loop to test general behavior and specific
optimizations
With the introduction of the output mux, the placing of the
last register inside the IOB is not possible anymore. Instead,
we now require a small input and output delay to ensuring
placement close to the PAD to minimize skew.
- Use wire type instead of reg type for fp_gpio_out/ddr in x300_core.
This allows adding an unbuffered mux later.
- Set width to correct size of 12 bits to avoid confusion.
Add another mux which controls if PS or user logic (=RFNoC)
controls the GPIO. The output is input to the master mux
which controls if Radio or PS/user logic controls the
GPIO.
