Wade Fife 2bc5131736 fpga: rfnoc: Add SKIP_WR_ACK_WAIT mode to axis_ctrl_master ... This adds an option to not require or wait for the AXIS-Ctrl packet response for CtrlPort writes. This is useful in cases where the writes are not critical (e.g., status updates) and occasional packet loss is expected. Enabling this feature will prevent the endpoint from hanging in situations where the AXIS-Ctrl write request or the write response is dropped on the network.		2026-02-12 11:33:54 -06:00
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export/x300/radio	Fix instances of sim preamble	2024-09-17 08:43:22 -05:00
lib	fpga: rfnoc: Add SKIP_WR_ACK_WAIT mode to axis_ctrl_master	2026-02-12 11:33:54 -06:00
sim	fpga: sim: Add wait_all_tb task to PkgTestExec	2025-12-10 20:22:40 -06:00
tools	fpga: tools: Add --include-dir to repeat_fpga_build	2026-01-13 12:38:50 +01:00
top	fpga: x4xx: remove unused JTAG engine from PS BD	2026-01-13 13:40:57 -06:00
.gitignore	Move ignore of build folders into top level	2025-07-18 11:19:52 +02:00
build.py	fpga: Replace references to python -> python3	2023-12-05 15:43:08 -06:00
LICENSE.md	Merge FPGA repository back into UHD repository	2020-01-28 09:35:36 -08:00