This adds support for the new USRP X420. It is the latest addition to
our X4xx series and comes with two HBX daughterboards. The HBX is
a one-channel direct conversion transceiver that covers 5G NR FR3 and
X-/KU-Band needs for Research and Prototyping in a frequency range of 10
MHz up to 20 GHz. It supports analog bandwidths of up to 1 GHz.
This commit is the UHD/host portion of the X420 support.
Co-authored-by: Martin Anderseck <martin.anderseck@emerson.com>
Co-authored-by: Ahmed Salman <ahmed.salman@emerson.com>
Co-authored-by: Max Köhler <max.koehler@emerson.com>
Co-authored-by: Markus Schill <markus.schill@emerson.com>
With this change, it is possible to have different sub-channels within
one channel to serve different purposes. For instance it is possible to
have one converter run in Real mode while two other converters serve I
and Q respectively. They all count as the same channel for UHD and the
driver software needs to take care to switch between them if required.
For the IQ architecture we also disable the NCO in the RFDC.
This enables the regmap to handle arrays properly. There are some
changes required to use this properly in MPM, but since the new
registers are not yet used by anything else, going without the MPM
changes doesn't do any harm, either. The array handling is basically a
Python copy of the C++ variant of the ZBX CPLD regmap.
FPGA:
- Split up MB registers that control daughterboard specific settings so
that daughterboards 0 and 1 could have different setings, in
preparation for future devices that require different settings.
This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
block/tile mapping of the individual channels, and information about
resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
them to their own headers, so it's trivial to add device-specific
sections of code instead for other devices in the future.
- This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
was unused and possibly broken.
- Move daughterboard-specific code into its own code location
(dboards/zbx)
- Move X410-specific register documentation to its own location
(doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
timekeeper)
MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
This commit refactors the existing register definitions, so that
duplicate entries don't get added to the get_all_addrs method.
Duplicates caused long builds on macOS/Clang, where build times
would go from sub 5 min to 50 min or more likely because
of the compiler trying to optimize.
Signed-off-by: Steven Koo <steven.koo@ni.com>
This adds support for read only registers in generated interfaces.
For this the default is extended to an option string. The old format
is still supported for backward compability, so if options string is
just a number it will be handled as a writable number.
The option string is a comma separated list with key=value pairs. The
value is optional and treated as None if missing.
common.py now allows to pass in **kwargs to the generate method which
is used by gen_zbx_cpld_regs.py to pass a filter function for registers
used by mpm only.
get_all_addr now has an additional (optional, defaults to false) flag
to indicate whether read only addresses are to be returned or not.
It also supports type generic for the result to align with
get_changed_addr function.
The ZBX CPLD CTRL map is adapted accordingly to reflect read only
registers. The power registers are flagged as MPM scope only (and not
used in ZBX CPLD control of UHD).
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Auto-generated IC Register Maps (e.g. magnesium_cpld_regs,
rhodium_cpld_regs, etc.) now provide getter methods for all attributes.
This gives access to the save state information for the device.
Signed-off-by: mattprost <matt.prost@ni.com>
For certain frequencies, the LMX2592 will sporadically fail to lock upon
the very first tune. When this happens, subsequent tunes (even to the same
frequency) do lock. This issue seems to be resolved by programming the FCAL
adjustment register fields (FCAL_LPFD_ADJ/FCAL_HPFD_ADJ) as described in
the LMX2592 datasheet. These fields adjust the FCAL calibration speed to
better accomodate PFD frequencies below 20MHz or above 100MHz.
This patch also fixes a few name typos in the register map that were
directly in the scope of this change.
This lets you declare registers like this:
REG_NAME[ARRAY_LEN] ADDRESS[BITS] DEFAULT ENUMS
The reg object will now carray REG_NAME as an array. So, you can do
regs.REG_NAME[0] = VALUE;
Add COMMON_PY_TMPL which is identical to COMMON_TMPL in functionality
but generates Python syntax rather than C++ header syntax. Modify the
generate function which will now determine if the destination regmap
file is a Python file or not and will use the appropriate template.
Updated Register values for ADF5356:
R2) Expand Frac2 to a 28-bit value for ADF5356
R6) Use negative bleed current for improved spurious performance
R7) Set Fractional-N Lock Detect Precision to 12.0 ns because of bleed
currents
R8) Use magic number for reserved bits
R9) Fix VCO Band Division calculation for ADF5356
RD) Expand Frac2 to a 28-bit value for ADF5356
Signed-off-by: mattprost <matt.prost@ni.com>
Letting garbage collection close the file works when using CPython, but
it fails with PyPy which uses a different garbage collection strategy.
This makes sure that the file is closed by using a file context manager.
This changes two things in all applicable files:
- Remove imports from __future__
- Change default shebangs from /usr/bin/env python to /usr/bin/env
python3
Without turning on tx power amplifer when being idle, the TX settling time is
100ms. Turning these power amplifiers on "all time" results in tx settling time
around 140us.
- Creates mpm/ subdirectory
- First pass at hardware daemon/MPM
- New code for LMK04828, AD9371
- spidev integration
Contributions by:
Martin Braun <martin.braun@ettus.com>
Derek Kozel <derek.kozel@ettus.com>
Mark Meserve <mark.meserve@ni.com>
Andrej Rode <andrej.rode@ettus.com>
ADF5355 and ADF5356 support merged into adf535x class
Default register values moved into regmap
Reviewed-By: Martin Braun <martin.braun@ettus.com>
Reviewed-By: Ashish Chaudhari <ashish@ettus.com>
Reviewed-By: Mark Meserve <mark.meserve@ni.com>
- Also removes all references to boost/cstdint.hpp and replaces it with
stdint.h (The 'correct' replacement would be <cstdint>, but not all of our
compilers support that).
- This function allows delaying divider pairs using the digital and analog
delay blocks in the LMK divider
- ctrl object caches delay for later retrieval
- Minor fixes to LMK regmap
