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ic_reg_maps: Add SPCC reg map
Add SPCC reg map for reference and testing.
This commit is contained in:
Toni Jones
Aaron Rossetto
parent
902f458137
commit
f2ae3e93f7
116
host/lib/ic_reg_maps/gen_spcc_regs.py
Executable file
116
host/lib/ic_reg_maps/gen_spcc_regs.py
Executable file
@ -0,0 +1,116 @@
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#
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# Copyright 2019 Ettus Research, a National Instruments Company
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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########################################################################
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# Template for raw text data describing registers
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# name addr[bit range inclusive] default optional enums
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########################################################################
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REGS_TMPL="""\
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########################################################################
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## Core Common
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########################################################################
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<% addr_0 = 0x0 %>\
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signature ${addr_0}[0:31] 0
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version ${addr_0+4}[0:31] 0
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instantiated ${addr_0+8}[0:31] 0
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########################################################################
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## JTAG 0
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########################################################################
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## No designated registers for the JTAG master
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########################################################################
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## UART 0 & 1
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########################################################################
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% for i in range(2):
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<% start_addr = addr_0 + 0x040 %>\
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<% addr = ((i*32) + start_addr) %>\
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clkdiv_uart${i} ${addr}[0:31] 0
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data_uart${i} ${addr+4}[0:31] 0
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txlvl_uart${i} ${addr+8}[0:31] 0
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rxlvl_uart${i} ${addr+12}[0:31] 0
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% endfor
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########################################################################
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## SPI 0, 1, 2, & 3
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########################################################################
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% for i in range(4):
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<% start_addr = addr_0 + 0x080 %>\
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<% addr = ((i*32) + start_addr) %>\
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rx_data_lo_spi${i} ${addr}[0:31] 0
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rx_data_hi_spi${i} ${addr+4}[0:31] 0
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~rx_data_spi${i} rx_data_lo_spi${i}, rx_data_hi_spi${i}
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tx_data_lo_spi${i} ${addr+8}[0:31] 0
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tx_data_hi_spi${i} ${addr+12}[0:31] 0
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~tx_data_spi${i} tx_data_lo_spi${i}, tx_data_hi_spi${i}
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ctrl_reg_spi${i} ${addr+16}[0:31] 0
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div_spi${i} ${addr+20}[0:31] 0
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ss_spi${i} ${addr+24}[0:31] 0
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% endfor
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########################################################################
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## GPIO ATR 0, 1, 2, & 3
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########################################################################
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% for i in range(4):
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<% start_addr = addr_0 + 0x100 %>\
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<% addr = ((i*32) + start_addr) %>\
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idled_gpio${i} ${addr}[0:31] 0
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rxd_gpio${i} ${addr+4}[0:31] 0
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txd_gpio${i} ${addr+8}[0:31] 0
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fdxd_gpio${i} ${addr+12}[0:31] 0
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ddr_gpio${i} ${addr+16}[0:31] 0
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atren_gpio${i} ${addr+20}[0:31] 0
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fabctrl_gpio${i} ${addr+24}[0:31] 0
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rb_gpio${i} ${addr+28}[0:31] 0
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% endfor
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########################################################################
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## I2C 0, 1, 2, & 3
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########################################################################
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% for i in range(4):
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<% start_addr = addr_0 + 0x180 %>\
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<% addr = ((i*32) + start_addr) %>\
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prerlo_i2c${i} ${addr}[0:31] 0
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prerhi_i2c${i} ${addr+4}[0:31] 0
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~prer_i2c${i} prerlo_i2c${i}, prerhi_i2c${i}
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ctrl_i2c${i} ${addr+8}[0:31] 0
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tx_i2c${i} ${addr+12}[0:31] 0
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rx_i2c${i} ${addr+16}[0:31] 0
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cmd_i2c${i} ${addr+20}[0:31] 0
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stat_i2c${i} ${addr+24}[0:31] 0
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% endfor
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"""
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########################################################################
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# Template for methods in the body of the struct
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########################################################################
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PY_BODY_TMPL = """\
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def get_reg(self, addr):
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reg = 0
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% for addr in sorted(set(map(lambda r: r.get_addr(), regs))):
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<% if_state = 'if' if loop.index == 0 else 'elif' %>${if_state} addr == ${addr}:
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% for reg in filter(lambda r: r.get_addr() == addr, regs):
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% if reg.get_enums():
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reg |= (self.${reg.get_name()}.value & ${reg.get_mask()}) << ${reg.get_shift()}
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% else:
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reg |= (self.${reg.get_name()} & ${reg.get_mask()}) << ${reg.get_shift()}
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% endif
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% endfor
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% endfor
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return reg
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def set_reg(self, addr, value):
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# writes value to a given address
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% for addr in sorted(set(map(lambda r: r.get_addr(), regs))):
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<% if_state = 'if' if loop.index == 0 else 'elif' %>${if_state} addr == ${addr}:
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% for reg in filter(lambda r: r.get_addr() == addr, regs):
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self.${reg.get_name()} = (value >> ${reg.get_shift()}) & ${reg.get_mask()}
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% endfor
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% endfor
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"""
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if __name__ == '__main__':
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import common; common.generate(
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name='spcc_regs',
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regs_tmpl=REGS_TMPL,
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py_body_tmpl=PY_BODY_TMPL,
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file=__file__,
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)
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@ -34,6 +34,10 @@ if(ENABLE_REGMAPS)
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${UHD_HOST_ROOT}/lib/ic_reg_maps/gen_lmk04816_regs.py
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${CMAKE_CURRENT_BINARY_DIR}/lmk04816_regs.py
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)
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REG_MAPS_GEN_SOURCE(
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${UHD_HOST_ROOT}/lib/ic_reg_maps/gen_spcc_regs.py
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${CMAKE_CURRENT_BINARY_DIR}/spcc_regs.py
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)
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# add an ic_reg_maps target which can be referenced outside of this subdirectory
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add_custom_target(ic_reg_maps DEPENDS ${IC_REG_MAPS})
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