The current firmware missed descriptors for B200-mini and
B205-mini. Added the missing descriptors.
Also this commit ammends the firmware howto. It specifies
the SDK version we are using as well as some additional
command applied to the SDK files to make the patch successful.
Co-authored-by: Lars Amsel <lars.amsel@emerson.com>
This is an upgrade to the latest FX3 SDK (1.3.5) and to the ARM gcc in
version 15.3.rel1 for the build of the B2xx firmware and bootloader. All
required steps are explained in the updated readme file.
Additionally, some bounds checks were added both in the firmware and the
bootloader, as well as some more validations and checks to prevent over-
and underflows. Newly introduced checks were documented in the code.
- Updated README with instructions on how to build using new SDK
(1.3.4 as of this change)
- Updated makefiles
- Updated memory map patch
Signed-off-by: michael-west <michael.west@ettus.com>
The address for the serial number was off by 2 bytes, causing a bad
value in the USB descriptor. This only occurred if the bootloader
image was loaded on the device.
Signed-off-by: michael-west <michael.west@ettus.com>
MASK_GPIO_SHDN_SW ( GPIO[52] ) should be shifted by "GPIO_SHDN_SW" but "GPIO_FX3_SCLK ".
Otherwise GPIOs of FX3 will initial GPIO_FX3_SCLK ( GPIO[53] ) as GPIO and SPI respectively.
It will make GPIO[53] conflict between SPI and GPIO, and SHDN_SW will not work properly as a power switch.
- Logging in conjunction with B200 side-channel utility
(using UART or directly over USB)
- More and better configurability, e.g. Tx voltage swing
and DMA configuration
- FX3 does not respond to AD9361 firmware transaction VREQs
- FX3 does not respond to AD9361 SPI transaction VREQs
- Deleted all AD9361 firmware files
- Bumped FW compat to 6
- Fix for BUG #485: B200: Channels Swap Between Runs
# Added code to transition state machine out of FDD while reconfiguring active chains.
# bb:0b9929 Mon Jun 16 14:56:26 2014 -0700
- Fix for BUG #500: B210: RX channels are not phase aligned
# Set bit to invert RX if internal LNA is bypassed
# bb:0a4565 Thu Jun 5 17:10:37 2014 -0700
- Switched to FPGA SPI engine
- Moved firmware AD9361 driver to UHD
- Bumped FW compat to 5, FPGA compat to 4
- Known Issue: AD9361 SPI rate is too slow
