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b2xx: Pulling FX3 and AD9361 source code into master.

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Ben Hilburn 2014-04-07 14:58:25 -07:00
parent 937eae5f48
commit 642f3fb582
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12
firmware/README.md
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@ -16,6 +16,18 @@ __Build Instructions:__
3. cmake `<source directory>`
4. make
## fx3/
__Description:__ This is the firmware for the FX3 USB PHY, and the AD9361 RFIC.
__Devices:__ USRP B200 and USRP B210
__Tools:__ Cypress FX3 SDK
__Build Instructions:__
Please see the `fx3/README.md` file for additional instructions.
## octoclock/
__Description:__ Firmware for the Octoclock device.

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INSTRUCTIONS
================================
# Building the B2xx FX3 Firmware
The USRP B200 and B210 each use the Cypress FX3 USB3 PHY for USB3 connectivity.
This device has an ARM core on it, which is programmed in C. This README will
show you how to build our firmware source
**A brief "Theory of Operations":**
The host sends commands to the FX3, our USB3 PHY, which has an on-board ARM
which runs the FX3 firmware code (hex file). That code translates commands into
SPI commands to/from the AD9361. The SPI lines run through the FPGA (bin or bit
file), where they are level-translated, and then head to the AD9361. Note that
the FPGA takes no action on these SPI lines. They are passive pass-throughs.
## Setting up the Cypress SDK
In order to compile the USRP B200 and B210 firmware, you will need the FX3 SDK
distributed by the FX3 manufacturer, Cypress Semiconductor. You can download the
[FX3 SDK from here](http://www.cypress.com/?rID=57990).
Once you have downloaded it, extract the ARM cross-compiler sub-directory from
the zip file and put it somewhere useful. The highest level directory you need
is `arm-2011.03/`.
Now that you have extracted the cross compilation toolchain, you need to set up
some environment variables to tell the B2xx `makefile` where to look for the
tools. These variables are:
```
$ export ARMGCC_INSTALL_PATH=<your path>/arm-2011.03
$ export ARMGCC_VERSION=4.5.2
```
Now, you'll need to set-up the Cypress SDK, as well. In the SDK, navigate to
the `firmware` directory, and copy the following sub-directories into
`uhd.git/firmware/fx3`: `common/`, `lpp_source/`, `u3p_firmware/`.
Your directory structure should now look like:
```
uhd.git/
|
--firmware/
|
--fx3/
|
--ad9361/ # From UHD
--b200/ # From UHD
--common/ # From Cypress SDK
--gpif2_designer/ # From UHD
--lpp_source/ # From Cypress SDK
--u3p_firmware/ # From Cypress SDK
--README.md # From UHD
```
## Applying the Patch to the Toolchain
Now, you'll need to apply a patch to a couple of files in the Cypress SDK. Head
into the `common/` directory you just copied from the Cypress SDK, and apply the
patch `b200/fx3_mem_map.patch`.
```
# cd uhd.git/firmware/common/
$ patch -p2 < ../b200/fx3_mem_map.patch
```
If you don't see any errors print on the screen, then the patch was successful.
## Building the Firmware
Now, you should be able to head into the `b200/` directory and simply build the
firmware:
```
$ cd uhd.git/firmware/fx3/b200
$ make
```
It will generate a `usrp_b200_fw.hex` file, which you can then give to UHD to
program your USRP B200 or USRP B210.

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//
// Copyright 2013-2014 Ettus Research LLC
//
#ifndef INCLUDED_AD9361_DISPATCH_H
#define INCLUDED_AD9361_DISPATCH_H
#include <ad9361_transaction.h>
extern void ad9361_dispatch(const char* request, char* response);
typedef void (*msgfn)(const char*, ...);
extern void ad9361_set_msgfn(msgfn pfn);
#endif /* INCLUDED_AD9361_DISPATCH_H */

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//
// Copyright 2013-2014 Ettus Research LLC
//
#ifndef INCLUDED_AD9361_TRANSACTION_H
#define INCLUDED_AD9361_TRANSACTION_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
//various constants
#define AD9361_TRANSACTION_VERSION 0x4
#define AD9361_DISPATCH_PACKET_SIZE 64
//action types
#define AD9361_ACTION_ECHO 0
#define AD9361_ACTION_INIT 1
#define AD9361_ACTION_SET_RX1_GAIN 2
#define AD9361_ACTION_SET_TX1_GAIN 3
#define AD9361_ACTION_SET_RX2_GAIN 4
#define AD9361_ACTION_SET_TX2_GAIN 5
#define AD9361_ACTION_SET_RX_FREQ 6
#define AD9361_ACTION_SET_TX_FREQ 7
#define AD9361_ACTION_SET_CODEC_LOOP 8
#define AD9361_ACTION_SET_CLOCK_RATE 9
#define AD9361_ACTION_SET_ACTIVE_CHAINS 10
static inline void ad9361_double_pack(const double input, uint32_t output[2])
{
const uint32_t *p = (const uint32_t *)&input;
output[0] = p[0];
output[1] = p[1];
}
static inline double ad9361_double_unpack(const uint32_t input[2])
{
double output = 0.0;
uint32_t *p = (uint32_t *)&output;
p[0] = input[0];
p[1] = input[1];
return output;
}
typedef struct
{
//version is expected to be AD9361_TRANSACTION_VERSION
//check otherwise for compatibility
uint32_t version;
//sequence number - increment every call for sanity
uint32_t sequence;
//action tells us what to do, see AD9361_ACTION_*
uint32_t action;
union
{
//enable mask for chains
uint32_t enable_mask;
//true to enable codec internal loopback
uint32_t codec_loop;
//freq holds request LO freq and result from tune
uint32_t freq[2];
//gain holds request gain and result from action
uint32_t gain[2];
//rate holds request clock rate and result from action
uint32_t rate[2];
} value;
//error message comes back as a reply -
//set to null string for no error \0
char error_msg[];
} ad9361_transaction_t;
#define AD9361_TRANSACTION_MAX_ERROR_MSG (AD9361_DISPATCH_PACKET_SIZE - (sizeof(ad9361_transaction_t)-4)-1) // -4 for 'error_msg' alignment padding, -1 for terminating \0
#ifdef __cplusplus
}
#endif
#endif /* INCLUDED_AD9361_TRANSACTION_H */

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//
// Copyright 2013-2014 Ettus Research LLC
//
#ifndef INCLUDED_AD9361_FILTER_TAPS_HPP
#define INCLUDED_AD9361_FILTER_TAPS_HPP
/* A default 128-tap filter that can be used for generic circumstances. */
static uint16_t default_128tap_coeffs[] = {
0x0001,0xfff1,0xffcf,0xffc0,0xffe8,0x0020,0x001a,0xffe3,
0xffe1,0x001f,0x0028,0xffdf,0xffcc,0x0024,0x0043,0xffdb,
0xffac,0x0026,0x0068,0xffdb,0xff80,0x0022,0x009a,0xffe2,
0xff47,0x0017,0x00db,0xfff3,0xfeff,0xffff,0x012b,0x0013,
0xfea5,0xffd7,0x0190,0x0046,0xfe35,0xff97,0x020e,0x0095,
0xfda7,0xff36,0x02ae,0x010d,0xfcf0,0xfea1,0x0383,0x01c6,
0xfbf3,0xfdb6,0x04b7,0x02f8,0xfa6d,0xfc1a,0x06be,0x0541,
0xf787,0xf898,0x0b60,0x0b6d,0xee88,0xea40,0x2786,0x7209
};
/* The below pair of filters is optimized for a 10MHz LTE application. */
/*
static uint16_t lte10mhz_rx_coeffs[] = {
0xffe2,0x0042,0x0024,0x0095,0x0056,0x004d,0xffcf,0xffb7,
0xffb1,0x0019,0x0059,0x006a,0x0004,0xff9d,0xff72,0xffd4,
0x0063,0x00b7,0x0062,0xffac,0xff21,0xff59,0x0032,0x0101,
0x00f8,0x0008,0xfeea,0xfeac,0xffa3,0x0117,0x01b5,0x00d0,
0xff05,0xfdea,0xfe9e,0x00ba,0x026f,0x0215,0xffb5,0xfd4a,
0xfd18,0xffa0,0x02de,0x03dc,0x0155,0xfd2a,0xfb0d,0xfd54,
0x0287,0x062f,0x048a,0xfe37,0xf862,0xf8c1,0x004d,0x0963,
0x0b88,0x02a4,0xf3e7,0xebdd,0xf5f8,0x1366,0x3830,0x518b
};
static uint16_t lte10mhz_tx_coeffs[] = {
0xfffb,0x0000,0x0004,0x0017,0x0024,0x0028,0x0013,0xfff3,
0xffdc,0xffe5,0x000b,0x0030,0x002e,0xfffe,0xffc4,0xffb8,
0xfff0,0x0045,0x0068,0x002b,0xffb6,0xff72,0xffad,0x0047,
0x00b8,0x0088,0xffc8,0xff1c,0xff33,0x001a,0x0110,0x0124,
0x0019,0xfec8,0xfe74,0xff9a,0x0156,0x0208,0x00d3,0xfe9b,
0xfd68,0xfe96,0x015d,0x033f,0x0236,0xfecd,0xfc00,0xfcb5,
0x00d7,0x04e5,0x04cc,0xffd5,0xf9fe,0xf8fb,0xfef2,0x078c,
0x0aae,0x036d,0xf5c0,0xed89,0xf685,0x12af,0x36a4,0x4faa
};
*/
#endif // INCLUDED_AD9361_FILTER_TAPS_HPP

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//
// Copyright 2013-2014 Ettus Research LLC
//
#ifndef INCLUDED_AD9361_GAIN_TABLES_HPP
#define INCLUDED_AD9361_GAIN_TABLES_HPP
uint8_t gain_table_sub_1300mhz[77][5] = { {0,0x00,0x00,0x20,1},
{1,0x00,0x00,0x00,0}, {2,0x00,0x00,0x00,0}, {3,0x00,0x01,0x00,0},
{4,0x00,0x02,0x00,0}, {5,0x00,0x03,0x00,0}, {6,0x00,0x04,0x00,0},
{7,0x00,0x05,0x00,0}, {8,0x01,0x03,0x20,1}, {9,0x01,0x04,0x00,0},
{10,0x01,0x05,0x00,0}, {11,0x01,0x06,0x00,0}, {12,0x01,0x07,0x00,0},
{13,0x01,0x08,0x00,0}, {14,0x01,0x09,0x00,0}, {15,0x01,0x0A,0x00,0},
{16,0x01,0x0B,0x00,0}, {17,0x01,0x0C,0x00,0}, {18,0x01,0x0D,0x00,0},
{19,0x01,0x0E,0x00,0}, {20,0x02,0x09,0x20,1}, {21,0x02,0x0A,0x00,0},
{22,0x02,0x0B,0x00,0}, {23,0x02,0x0C,0x00,0}, {24,0x02,0x0D,0x00,0},
{25,0x02,0x0E,0x00,0}, {26,0x02,0x0F,0x00,0}, {27,0x02,0x10,0x00,0},
{28,0x02,0x2B,0x20,1}, {29,0x02,0x2C,0x00,0}, {30,0x04,0x27,0x20,1},
{31,0x04,0x28,0x00,0}, {32,0x04,0x29,0x00,0}, {33,0x04,0x2A,0x00,0},
{34,0x04,0x2B,0x00,1}, {35,0x24,0x21,0x20,0}, {36,0x24,0x22,0x00,1},
{37,0x44,0x20,0x20,0}, {38,0x44,0x21,0x00,0}, {39,0x44,0x22,0x00,0},
{40,0x44,0x23,0x00,0}, {41,0x44,0x24,0x00,0}, {42,0x44,0x25,0x00,0},
{43,0x44,0x26,0x00,0}, {44,0x44,0x27,0x00,0}, {45,0x44,0x28,0x00,0},
{46,0x44,0x29,0x00,0}, {47,0x44,0x2A,0x00,0}, {48,0x44,0x2B,0x00,0},
{49,0x44,0x2C,0x00,0}, {50,0x44,0x2D,0x00,0}, {51,0x44,0x2E,0x00,0},
{52,0x44,0x2F,0x00,0}, {53,0x44,0x30,0x00,0}, {54,0x44,0x31,0x00,0},
{55,0x64,0x2E,0x20,1}, {56,0x64,0x2F,0x00,0}, {57,0x64,0x30,0x00,0},
{58,0x64,0x31,0x00,0}, {59,0x64,0x32,0x00,0}, {60,0x64,0x33,0x00,0},
{61,0x64,0x34,0x00,0}, {62,0x64,0x35,0x00,0}, {63,0x64,0x36,0x00,0},
{64,0x64,0x37,0x00,0}, {65,0x64,0x38,0x00,0}, {66,0x65,0x38,0x20,1},
{67,0x66,0x38,0x20,1}, {68,0x67,0x38,0x20,1}, {69,0x68,0x38,0x20,1},
{70,0x69,0x38,0x20,1}, {71,0x6A,0x38,0x20,1}, {72,0x6B,0x38,0x20,1},
{73,0x6C,0x38,0x20,1}, {74,0x6D,0x38,0x20,1}, {75,0x6E,0x38,0x20,1},
{76,0x6F,0x38,0x20,1}};
uint8_t gain_table_1300mhz_to_4000mhz[77][5] = { {0,0x00,0x00,0x20,1},
{1,0x00,0x00,0x00,0}, {2,0x00,0x00,0x00,0}, {3,0x00,0x01,0x00,0},
{4,0x00,0x02,0x00,0}, {5,0x00,0x03,0x00,0}, {6,0x00,0x04,0x00,0},
{7,0x00,0x05,0x00,0}, {8,0x01,0x03,0x20,1}, {9,0x01,0x04,0x00,0},
{10,0x01,0x05,0x00,0}, {11,0x01,0x06,0x00,0}, {12,0x01,0x07,0x00,0},
{13,0x01,0x08,0x00,0}, {14,0x01,0x09,0x00,0}, {15,0x01,0x0A,0x00,0},
{16,0x01,0x0B,0x00,0}, {17,0x01,0x0C,0x00,0}, {18,0x01,0x0D,0x00,0},
{19,0x01,0x0E,0x00,0}, {20,0x02,0x09,0x20,1}, {21,0x02,0x0A,0x00,0},
{22,0x02,0x0B,0x00,0}, {23,0x02,0x0C,0x00,0}, {24,0x02,0x0D,0x00,0},
{25,0x02,0x0E,0x00,0}, {26,0x02,0x0F,0x00,0}, {27,0x02,0x10,0x00,0},
{28,0x02,0x2B,0x20,1}, {29,0x02,0x2C,0x00,0}, {30,0x04,0x28,0x20,1},
{31,0x04,0x29,0x00,0}, {32,0x04,0x2A,0x00,0}, {33,0x04,0x2B,0x00,0},
{34,0x24,0x20,0x20,0}, {35,0x24,0x21,0x00,1}, {36,0x44,0x20,0x20,0},
{37,0x44,0x21,0x00,1}, {38,0x44,0x22,0x00,0}, {39,0x44,0x23,0x00,0},
{40,0x44,0x24,0x00,0}, {41,0x44,0x25,0x00,0}, {42,0x44,0x26,0x00,0},
{43,0x44,0x27,0x00,0}, {44,0x44,0x28,0x00,0}, {45,0x44,0x29,0x00,0},
{46,0x44,0x2A,0x00,0}, {47,0x44,0x2B,0x00,0}, {48,0x44,0x2C,0x00,0},
{49,0x44,0x2D,0x00,0}, {50,0x44,0x2E,0x00,0}, {51,0x44,0x2F,0x00,0},
{52,0x44,0x30,0x00,0}, {53,0x44,0x31,0x00,0}, {54,0x44,0x32,0x00,0},
{55,0x64,0x2E,0x20,1}, {56,0x64,0x2F,0x00,0}, {57,0x64,0x30,0x00,0},
{58,0x64,0x31,0x00,0}, {59,0x64,0x32,0x00,0}, {60,0x64,0x33,0x00,0},
{61,0x64,0x34,0x00,0}, {62,0x64,0x35,0x00,0}, {63,0x64,0x36,0x00,0},
{64,0x64,0x37,0x00,0}, {65,0x64,0x38,0x00,0}, {66,0x65,0x38,0x20,1},
{67,0x66,0x38,0x20,1}, {68,0x67,0x38,0x20,1}, {69,0x68,0x38,0x20,1},
{70,0x69,0x38,0x20,1}, {71,0x6A,0x38,0x20,1}, {72,0x6B,0x38,0x20,1},
{73,0x6C,0x38,0x20,1}, {74,0x6D,0x38,0x20,1}, {75,0x6E,0x38,0x20,1},
{76,0x6F,0x38,0x20,1}};
uint8_t gain_table_4000mhz_to_6000mhz[77][5] = { {0,0x00,0x00,0x20,1},
{1,0x00,0x00,0x00,0}, {2,0x00,0x00,0x00,0}, {3,0x00,0x00,0x00,0},
{4,0x00,0x00,0x00,0}, {5,0x00,0x01,0x00,0}, {6,0x00,0x02,0x00,0},
{7,0x00,0x03,0x00,0}, {8,0x01,0x01,0x20,1}, {9,0x01,0x02,0x00,0},
{10,0x01,0x03,0x00,0}, {11,0x01,0x04,0x20,1}, {12,0x01,0x05,0x00,0},
{13,0x01,0x06,0x00,0}, {14,0x01,0x07,0x00,0}, {15,0x01,0x08,0x00,0},
{16,0x01,0x09,0x00,0}, {17,0x01,0x0A,0x00,0}, {18,0x01,0x0B,0x00,0},
{19,0x01,0x0C,0x00,0}, {20,0x02,0x08,0x20,1}, {21,0x02,0x09,0x00,0},
{22,0x02,0x0A,0x00,0}, {23,0x02,0x0B,0x20,1}, {24,0x02,0x0C,0x00,0},
{25,0x02,0x0D,0x00,0}, {26,0x02,0x0E,0x00,0}, {27,0x02,0x0F,0x00,0},
{28,0x02,0x2A,0x20,1}, {29,0x02,0x2B,0x00,0}, {30,0x04,0x27,0x20,1},
{31,0x04,0x28,0x00,0}, {32,0x04,0x29,0x00,0}, {33,0x04,0x2A,0x00,0},
{34,0x04,0x2B,0x00,0}, {35,0x04,0x2C,0x00,0}, {36,0x04,0x2D,0x00,0},
{37,0x24,0x20,0x20,1}, {38,0x24,0x21,0x00,0}, {39,0x24,0x22,0x00,0},
{40,0x44,0x20,0x20,1}, {41,0x44,0x21,0x00,0}, {42,0x44,0x22,0x00,0},
{43,0x44,0x23,0x00,0}, {44,0x44,0x24,0x00,0}, {45,0x44,0x25,0x00,0},
{46,0x44,0x26,0x00,0}, {47,0x44,0x27,0x00,0}, {48,0x44,0x28,0x00,0},
{49,0x44,0x29,0x00,0}, {50,0x44,0x2A,0x00,0}, {51,0x44,0x2B,0x00,0},
{52,0x44,0x2C,0x00,0}, {53,0x44,0x2D,0x00,0}, {54,0x44,0x2E,0x00,0},
{55,0x64,0x2E,0x20,1}, {56,0x64,0x2F,0x00,0}, {57,0x64,0x30,0x00,0},
{58,0x64,0x31,0x00,0}, {59,0x64,0x32,0x00,0}, {60,0x64,0x33,0x00,0},
{61,0x64,0x34,0x00,0}, {62,0x64,0x35,0x00,0}, {63,0x64,0x36,0x00,0},
{64,0x64,0x37,0x00,0}, {65,0x64,0x38,0x00,0}, {66,0x65,0x38,0x20,1},
{67,0x66,0x38,0x20,1}, {68,0x67,0x38,0x20,1}, {69,0x68,0x38,0x20,1},
{70,0x69,0x38,0x20,1}, {71,0x6A,0x38,0x20,1}, {72,0x6B,0x38,0x20,1},
{73,0x6C,0x38,0x20,1}, {74,0x6D,0x38,0x20,1}, {75,0x6E,0x38,0x20,1},
{76,0x6F,0x38,0x20,1}};
#endif /* INCLUDED_AD9361_GAIN_TABLES_HPP */

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//
// Copyright 2013-2014 Ettus Research LLC
//
#ifndef INCLUDED_AD9361_SYNTH_LUT_HPP
#define INCLUDED_AD9361_SYNTH_LUT_HPP
double vco_index[53] = {12605000000, 12245000000, 11906000000, 11588000000,
11288000000, 11007000000, 10742000000, 10492000000,
10258000000, 10036000000, 9827800000, 9631100000,
9445300000, 9269800000, 9103600000, 8946300000,
8797000000, 8655300000, 8520600000, 8392300000,
8269900000, 8153100000, 8041400000, 7934400000,
7831800000, 7733200000, 7638400000, 7547100000,
7459000000, 7374000000, 7291900000, 7212400000,
7135500000, 7061000000, 6988700000, 6918600000,
6850600000, 6784600000, 6720500000, 6658200000,
6597800000, 6539200000, 6482300000, 6427000000,
6373400000, 6321400000, 6270900000, 6222000000,
6174500000, 6128400000, 6083600000, 6040100000,
5997700000};
int synth_cal_lut[53][12] = { {10, 0, 4, 0, 15, 8, 8, 13, 4, 13, 15, 9},
{10, 0, 4, 0, 15, 8, 9, 13, 4, 13, 15, 9},
{10, 0, 4, 0, 15, 8, 10, 13, 4, 13, 15, 9},
{10, 0, 4, 0, 15, 8, 11, 13, 4, 13, 15, 9},
{10, 0, 4, 0, 15, 8, 11, 13, 4, 13, 15, 9},
{10, 0, 4, 0, 14, 8, 12, 13, 4, 13, 15, 9},
{10, 0, 4, 0, 14, 8, 13, 13, 4, 13, 15, 9},
{10, 0, 5, 1, 14, 9, 13, 13, 4, 13, 15, 9},
{10, 0, 5, 1, 14, 9, 14, 13, 4, 13, 15, 9},
{10, 0, 5, 1, 14, 9, 15, 13, 4, 13, 15, 9},
{10, 0, 5, 1, 14, 9, 15, 13, 4, 13, 15, 9},
{10, 0, 5, 1, 13, 9, 16, 13, 4, 13, 15, 9},
{10, 0, 5, 1, 13, 9, 17, 13, 4, 13, 15, 9},
{10, 0, 5, 1, 13, 9, 18, 13, 4, 13, 15, 9},
{10, 0, 5, 1, 13, 9, 18, 13, 4, 13, 15, 9},
{10, 0, 5, 1, 13, 9, 19, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 14, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 14, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 15, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 15, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 16, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 16, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 17, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 17, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 18, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 18, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 19, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 19, 13, 4, 13, 15, 9},
{10, 1, 6, 1, 15, 11, 20, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 12, 20, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 12, 21, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 12, 21, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 22, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 22, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 23, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 23, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 24, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 24, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 25, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 25, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 26, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 26, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 27, 13, 4, 13, 15, 9},
{10, 1, 7, 2, 15, 14, 27, 13, 4, 13, 15, 9},
{10, 3, 7, 3, 15, 12, 18, 13, 4, 13, 15, 9},
{10, 3, 7, 3, 15, 12, 18, 13, 4, 13, 15, 9},
{10, 3, 7, 3, 15, 12, 18, 13, 4, 13, 15, 9},
{10, 3, 7, 3, 15, 12, 19, 13, 4, 13, 15, 9},
{10, 3, 7, 3, 15, 12, 19, 13, 4, 13, 15, 9},
{10, 3, 7, 3, 15, 12, 19, 13, 4, 13, 15, 9},
{10, 3, 7, 3, 15, 12, 19, 13, 4, 13, 15, 9},
{10, 3, 7, 3, 15, 12, 20, 13, 4, 13, 15, 9},
{10, 3, 7, 3, 15, 12, 20, 13, 4, 13, 15, 9}};
#if 0 /* This is the table for a 40MHz RFPLL Reference */
int synth_cal_lut[53][12] = { {10, 0, 4, 0, 15, 8, 8, 12, 3, 14, 15, 11},
{10, 0, 4, 0, 15, 8, 9, 12, 3, 14, 15, 11},
{10, 0, 4, 0, 15, 8, 9, 12, 3, 14, 15, 11},
{10, 0, 4, 0, 15, 8, 10, 12, 3, 14, 15, 11},
{10, 0, 4, 0, 15, 8, 11, 12, 3, 14, 15, 11},
{10, 0, 4, 0, 15, 8, 11, 12, 3, 14, 15, 11},
{10, 0, 4, 0, 14, 8, 12, 12, 3, 14, 15, 11},
{10, 0, 5, 1, 14, 9, 13, 12, 3, 14, 15, 11},
{10, 0, 5, 1, 14, 9, 13, 12, 3, 14, 15, 11},
{10, 0, 5, 1, 14, 9, 14, 12, 3, 14, 15, 11},
{10, 0, 5, 1, 14, 9, 15, 12, 3, 14, 15, 11},
{10, 0, 5, 1, 14, 9, 15, 12, 3, 14, 15, 11},
{10, 0, 5, 1, 14, 9, 16, 12, 3, 14, 15, 11},
{10, 0, 5, 1, 14, 9, 17, 12, 3, 14, 15, 11},
{10, 0, 5, 1, 14, 9, 17, 12, 3, 14, 15, 11},
{10, 0, 5, 1, 14, 9, 18, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 13, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 14, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 14, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 15, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 15, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 16, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 16, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 17, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 17, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 17, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 18, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 18, 12, 3, 14, 15, 11},
{10, 1, 6, 1, 15, 11, 19, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 12, 19, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 12, 20, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 12, 20, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 21, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 21, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 22, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 22, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 23, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 23, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 24, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 24, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 25, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 25, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 26, 12, 3, 14, 15, 11},
{10, 1, 7, 2, 15, 14, 26, 12, 3, 14, 15, 11},
{10, 3, 7, 3, 15, 12, 17, 12, 3, 14, 15, 11},
{10, 3, 7, 3, 15, 12, 17, 12, 3, 14, 15, 11},
{10, 3, 7, 3, 15, 12, 17, 12, 3, 14, 15, 11},
{10, 3, 7, 3, 15, 12, 18, 12, 3, 14, 15, 11},
{10, 3, 7, 3, 15, 12, 18, 12, 3, 14, 15, 11},
{10, 3, 7, 3, 15, 12, 18, 12, 3, 14, 15, 11},
{10, 3, 7, 3, 15, 12, 18, 12, 3, 14, 15, 11},
{10, 3, 7, 3, 15, 12, 19, 12, 3, 14, 15, 11},
{10, 3, 7, 3, 15, 12, 19, 12, 3, 14, 15, 11} };
#endif
#endif /* INCLUDED_AD9361_SYNTH_LUT_HPP */

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*.o
*.elf
*.hex
*.map

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//
// Copyright 2013-2014 Ettus Research LLC
//
#include "cyu3error.h"
#include "cyu3i2c.h"
#include "cyu3spi.h"
#include "cyu3os.h"
#include "cyu3pib.h"
#include "cyu3system.h"
#include "cyu3usb.h"
#include "cyu3utils.h"
#include "pib_regs.h"
#include "b200_vrq.h"
#include <stdint.h>
#define true CyTrue
#define false CyFalse
typedef CyBool_t bool;
/* Fast sqrt() - precision can be improved by increasing
* the number of iterations
*/
float ad9361_sqrt(const float number)
{
uint32_t i;
float x2, y;
x2 = number * 0.5F;
y = number;
i = *(uint32_t *) &y;
i = 0x5f3759df - ( i >> 1 );
y = *(float *) &i;
y = y * (1.5F - (x2 * y * y));
return number * y;
}
void ad9361_msleep(const unsigned millis)
{
CyU3PThreadSleep(millis);
}
#define AD9361_MIN(a, b) CY_U3P_MIN(a, b)
#define AD9361_MAX(a, b) CY_U3P_MAX(a, b)
#define AD9361_CEIL_INT(a) ((int)(a+1))
#define AD9361_FLOOR_INT(a) ((int)(a))
#define AD9361_CLOCKING_MODE 0
#define AD9361_RX_BAND_EDGE0 2.2e9
#define AD9361_RX_BAND_EDGE1 4e9
#define AD9361_TX_BAND_EDGE 2.5e9
#include "../ad9361/lib/ad9361_impl.c"

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//
// Copyright 2013-2014 Ettus Research LLC
//
/*
* Project Name: b200_v2.cyfx
* Time : 01/17/2013 12:50:08
* Device Type: FX3
* Project Type: GPIF2
*
*
*
*
* This is a generated file and should not be modified
* This file need to be included only once in the firmware
* This file is generated by Gpif2 designer tool version - 1.0.715.0
*
*/
#ifndef _INCLUDED_CYFXGPIF2CONFIG_
#define _INCLUDED_CYFXGPIF2CONFIG_
#include "cyu3types.h"
#include "cyu3gpif.h"
/* Summary
Number of states in the state machine
*/
#define CY_NUMBER_OF_STATES 6
/* Summary
Mapping of user defined state names to state indices
*/
#define RESET 0
#define IDLE 1
#define READ 2
#define WRITE 3
#define SHORT_PKT 4
#define ZLP 5
/* Summary
Initial value of early outputs from the state machine.
*/
#define ALPHA_RESET 0x8
/* Summary
Transition function values used in the state machine.
*/
uint16_t CyFxGpifTransition[] = {
0x0000, 0x8080, 0x2222, 0x5555, 0x7F7F, 0x1F1F, 0x8888
};
/* Summary
Table containing the transition information for various states.
This table has to be stored in the WAVEFORM Registers.
This array consists of non-replicated waveform descriptors and acts as a
waveform table.
*/
CyU3PGpifWaveData CyFxGpifWavedata[] = {
{{0x1E086001,0x000100C4,0x80000000},{0x00000000,0x00000000,0x00000000}},
{{0x4E080302,0x00000200,0x80000000},{0x00000000,0x00000000,0x00000000}},
{{0x1E086001,0x000100C4,0x80000000},{0x4E040704,0x20000200,0xC0100000}},
{{0x00000000,0x00000000,0x00000000},{0x00000000,0x00000000,0x00000000}},
{{0x00000000,0x00000000,0x00000000},{0x3E738705,0x00000200,0xC0100000}},
{{0x00000000,0x00000000,0x00000000},{0x5E002703,0x2001020C,0x80000000}},
{{0x00000000,0x00000000,0x00000000},{0x4E040704,0x20000200,0xC0100000}}
};
/* Summary
Table that maps state indices to the descriptor table indices.
*/
uint8_t CyFxGpifWavedataPosition[] = {
0,1,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
0,4,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
0,5,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
0,6,0,2,0,0
};
/* Summary
GPIF II configuration register values.
*/
uint32_t CyFxGpifRegValue[] = {
0x80000380, /* CY_U3P_PIB_GPIF_CONFIG */
0x000010AC, /* CY_U3P_PIB_GPIF_BUS_CONFIG */
0x01070002, /* CY_U3P_PIB_GPIF_BUS_CONFIG2 */
0x00000044, /* CY_U3P_PIB_GPIF_AD_CONFIG */
0x00000000, /* CY_U3P_PIB_GPIF_STATUS */
0x00000000, /* CY_U3P_PIB_GPIF_INTR */
0x00000000, /* CY_U3P_PIB_GPIF_INTR_MASK */
0x00000082, /* CY_U3P_PIB_GPIF_SERIAL_IN_CONFIG */
0x00000782, /* CY_U3P_PIB_GPIF_SERIAL_OUT_CONFIG */
0x00000500, /* CY_U3P_PIB_GPIF_CTRL_BUS_DIRECTION */
0x0000FFCF, /* CY_U3P_PIB_GPIF_CTRL_BUS_DEFAULT */
0x000000BF, /* CY_U3P_PIB_GPIF_CTRL_BUS_POLARITY */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_TOGGLE */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000018, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000019, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000006, /* CY_U3P_PIB_GPIF_CTRL_COUNT_CONFIG */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COUNT_RESET */
0x0000FFFF, /* CY_U3P_PIB_GPIF_CTRL_COUNT_LIMIT */
0x0000010A, /* CY_U3P_PIB_GPIF_ADDR_COUNT_CONFIG */
0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COUNT_RESET */
0x0000FFFF, /* CY_U3P_PIB_GPIF_ADDR_COUNT_LIMIT */
0x00000000, /* CY_U3P_PIB_GPIF_STATE_COUNT_CONFIG */
0x0000FFFF, /* CY_U3P_PIB_GPIF_STATE_COUNT_LIMIT */
0x0000010A, /* CY_U3P_PIB_GPIF_DATA_COUNT_CONFIG */
0x00000000, /* CY_U3P_PIB_GPIF_DATA_COUNT_RESET */
0x0000FFFF, /* CY_U3P_PIB_GPIF_DATA_COUNT_LIMIT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COMP_VALUE */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COMP_MASK */
0x00000000, /* CY_U3P_PIB_GPIF_DATA_COMP_VALUE */
0x00000000, /* CY_U3P_PIB_GPIF_DATA_COMP_MASK */
0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COMP_VALUE */
0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COMP_MASK */
0x00000000, /* CY_U3P_PIB_GPIF_DATA_CTRL */
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
0x80010400, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
0x80010401, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
0x80010402, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
0x80010403, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
0x00000000, /* CY_U3P_PIB_GPIF_LAMBDA_STAT */
0x00000000, /* CY_U3P_PIB_GPIF_ALPHA_STAT */
0x00000000, /* CY_U3P_PIB_GPIF_BETA_STAT */
0x00080000, /* CY_U3P_PIB_GPIF_WAVEFORM_CTRL_STAT */
0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_SWITCH */
0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_SWITCH_TIMEOUT */
0x00000000, /* CY_U3P_PIB_GPIF_CRC_CONFIG */
0x00000000, /* CY_U3P_PIB_GPIF_CRC_DATA */
0xFFFFFFF1 /* CY_U3P_PIB_GPIF_BETA_DEASSERT */
};
/* Summary
This structure holds all the configuration inputs for the GPIF II.
*/
const CyU3PGpifConfig_t CyFxGpifConfig = {
(uint16_t)(sizeof(CyFxGpifWavedataPosition)/sizeof(uint8_t)),
CyFxGpifWavedata,
CyFxGpifWavedataPosition,
(uint16_t)(sizeof(CyFxGpifTransition)/sizeof(uint16_t)),
CyFxGpifTransition,
(uint16_t)(sizeof(CyFxGpifRegValue)/sizeof(uint32_t)),
CyFxGpifRegValue
};
#endif /* _INCLUDED_CYFXGPIF2CONFIG_ */

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//
// Copyright 2013-2014 Ettus Research LLC
//
#include "b200_i2c.h"
#include "cyu3i2c.h"
/* I2c initialization for EEPROM programming. */
void CyFxI2cInit (uint16_t pageLen) {
CyU3PI2cConfig_t i2cConfig;
/* Initialize and configure the I2C master module. */
CyU3PI2cInit ();
/* Start the I2C master block. The bit rate is set at 100KHz.
* The data transfer is done via DMA. */
CyU3PMemSet ((uint8_t *)&i2cConfig, 0, sizeof(i2cConfig));
i2cConfig.bitRate = CY_FX_USBI2C_I2C_BITRATE;
i2cConfig.busTimeout = 0xFFFFFFFF;
i2cConfig.dmaTimeout = 0xFFFF;
i2cConfig.isDma = CyFalse;
CyU3PI2cSetConfig (&i2cConfig, NULL);
glI2cPageSize = pageLen;
}
/* I2C read / write for programmer application. */
void CyFxUsbI2cTransfer (
uint16_t byteAddress,
uint8_t devAddr,
uint16_t byteCount,
uint8_t *buffer,
CyBool_t isRead)
{
CyU3PI2cPreamble_t preamble;
uint16_t pageCount = (byteCount / glI2cPageSize);
uint16_t resCount = glI2cPageSize;
if (byteCount == 0) {
return;
}
if ((byteCount % glI2cPageSize) != 0) {
pageCount ++;
resCount = byteCount % glI2cPageSize;
}
while (pageCount != 0) {
if (isRead) {
/* Update the preamble information. */
preamble.length = 4;
preamble.buffer[0] = devAddr;
preamble.buffer[1] = (uint8_t)(byteAddress >> 8);
preamble.buffer[2] = (uint8_t)(byteAddress & 0xFF);
preamble.buffer[3] = (devAddr | 0x01);
preamble.ctrlMask = 0x0004;
CyU3PI2cReceiveBytes (&preamble, buffer, (pageCount == 1) ? resCount : glI2cPageSize, 0);
} else {
/* Write. Update the preamble information. */
preamble.length = 3;
preamble.buffer[0] = devAddr;
preamble.buffer[1] = (uint8_t)(byteAddress >> 8);
preamble.buffer[2] = (uint8_t)(byteAddress & 0xFF);
preamble.ctrlMask = 0x0000;
CyU3PI2cTransmitBytes (&preamble, buffer, (pageCount == 1) ? resCount : glI2cPageSize, 0);
/* Wait for the write to complete. */
preamble.length = 1;
CyU3PI2cWaitForAck(&preamble, 200);
}
/* An additional delay seems to be required after receiving an ACK. */
CyU3PThreadSleep (1);
/* Update the parameters */
byteAddress += glI2cPageSize;
buffer += glI2cPageSize;
pageCount --;
}
}

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//
// Copyright 2013-2014 Ettus Research LLC
//
#ifndef _B200_I2C_H
#define _B200_I2C_H
#include "cyu3externcstart.h"
#include "cyu3usbconst.h"
#include "cyu3types.h"
/* Following two definitions made in b200_main.h for consistency. */
/* define B200_VREQ_EEPROM_WRITE (uint8_t)(0xBA) */
/* define B200_VREQ_EEPROM_READ (uint8_t)(0xBB) */
static uint16_t glI2cPageSize = 0x40; /* I2C Page size to be used for transfers. */
/* This application uses EEPROM as the slave I2C device. The I2C EEPROM
* part number used is 24LC256. The capacity of the EEPROM is 256K bits */
#define CY_FX_USBI2C_I2C_MAX_CAPACITY (32 * 1024) /* Capacity in bytes */
/* The following constant is defined based on the page size that the I2C
* device support. 24LC256 support 64 byte page write access. */
#define CY_FX_USBI2C_I2C_PAGE_SIZE (64)
/* I2C Data rate */
#define CY_FX_USBI2C_I2C_BITRATE (100000)
/* Give a timeout value of 5s for any programming. */
#define CY_FX_USB_I2C_TIMEOUT (5000)
/* Function forward-declerations. */
void CyFxI2cInit (uint16_t pageLen);
void CyFxUsbI2cTransfer (uint16_t byteAddress, uint8_t devAddr,
uint16_t byteCount, uint8_t *buffer, CyBool_t isRead);
#include "cyu3externcend.h"
#endif /* _B200_I2C_H */

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//
// Copyright 2013-2014 Ettus Research LLC
//
#ifndef _B200_MAIN_H
#define _B200_MAIN_H
#include "cyu3externcstart.h"
#include "cyu3types.h"
#include "cyu3usbconst.h"
#define FX3_COMPAT_MAJOR (uint8_t)(4)
#define FX3_COMPAT_MINOR (uint8_t)(0)
/* GPIO Pins */
#define GPIO_FPGA_RESET (uint32_t)(26) // CTL[9]
#define GPIO_DONE (uint32_t)(27)
#define GPIO_PROGRAM_B (uint32_t)(45)
#define GPIO_INIT_B (uint32_t)(50)
#define GPIO_AUX_PWR_ON (uint32_t)(51)
#define GPIO_SHDN_SW (uint32_t)(52)
#define GPIO_FX3_SCLK (uint32_t)(53)
#define GPIO_FX3_CE (uint32_t)(54)
#define GPIO_FX3_MISO (uint32_t)(55)
#define GPIO_FX3_MOSI (uint32_t)(56)
#define GPIO_FPGA_SB_SCL (uint32_t)(25) // CTL[8]
#define GPIO_FPGA_SB_SDA (uint32_t)(23) // CTL[6]
/* Create the bit-shifts that define the above GPIOs for bitmaps. The bitshifts
* are relative to 32-bit masks, so shifts > 32 are adjusted accordingly. Note
* that GPIOs < 32 are configured without the use of masks. */
#define MASK_GPIO_PROGRAM_B (uint32_t)(1 << (GPIO_PROGRAM_B - 32))
#define MASK_GPIO_INIT_B (uint32_t)(1 << (GPIO_INIT_B - 32))
#define MASK_GPIO_AUX_PWR_ON (uint32_t)(1 << (GPIO_FX3_SCLK - 32))
#define MASK_GPIO_SHDN_SW (uint32_t)(1 << (GPIO_FX3_SCLK - 32))
#define MASK_GPIO_FX3_SCLK (uint32_t)(1 << (GPIO_FX3_SCLK - 32))
#define MASK_GPIO_FX3_CE (uint32_t)(1 << (GPIO_FX3_CE - 32))
#define MASK_GPIO_FX3_MISO (uint32_t)(1 << (GPIO_FX3_MISO - 32))
#define MASK_GPIO_FX3_MOSI (uint32_t)(1 << (GPIO_FX3_MOSI - 32))
#define MASK_GPIO_FPGA_SB_SCL (uint32_t)(1 << (GPIO_FPGA_SB_SCL - 0))
#define MASK_GPIO_FPGA_SB_SDA (uint32_t)(1 << (GPIO_FPGA_SB_SDA - 0))
#define USB3_PACKETS_PER_BURST (16)
#define USB2_PACKETS_PER_BURST (1)
#define DMA_SIZE_INFINITE (0)
#define APP_THREAD_STACK_SIZE (0x0800)
#define THREAD_PRIORITY (8)
#define B200_VREQ_BITSTREAM_START (uint8_t)(0x02)
#define B200_VREQ_BITSTREAM_DATA (uint8_t)(0x12)
#define B200_VREQ_BITSTREAM_DATA_FILL (uint8_t)(0x13)
#define B200_VREQ_BITSTREAM_DATA_COMMIT (uint8_t)(0x14)
#define B200_VREQ_GET_COMPAT (uint8_t)(0x15)
#define B200_VREQ_SET_FPGA_HASH (uint8_t)(0x1C)
#define B200_VREQ_GET_FPGA_HASH (uint8_t)(0x1D)
#define B200_VREQ_SET_FW_HASH (uint8_t)(0x1E)
#define B200_VREQ_GET_FW_HASH (uint8_t)(0x1F)
#define B200_VREQ_LOOP_CODE (uint8_t)(0x22)
#define B200_VREQ_GET_LOG (uint8_t)(0x23)
#define B200_VREQ_GET_COUNTERS (uint8_t)(0x24)
#define B200_VREQ_CLEAR_COUNTERS (uint8_t)(0x25)
#define B200_VREQ_GET_USB_EVENT_LOG (uint8_t)(0x26)
#define B200_VREQ_SET_CONFIG (uint8_t)(0x27)
#define B200_VREQ_GET_CONFIG (uint8_t)(0x28)
#define B200_VREQ_WRITE_SB (uint8_t)(0x29)
#define B200_VREQ_SET_SB_BAUD_DIV (uint8_t)(0x30)
#define B200_VREQ_FLUSH_DATA_EPS (uint8_t)(0x31)
#define B200_VREQ_SPI_WRITE_AD9361 (uint8_t)(0x32)
#define B200_VREQ_SPI_READ_AD9361 (uint8_t)(0x42)
#define B200_VREQ_FPGA_CONFIG (uint8_t)(0x55)
#define B200_VREQ_TOGGLE_FPGA_RESET (uint8_t)(0x62)
#define B200_VREQ_TOGGLE_GPIF_RESET (uint8_t)(0x72)
#define B200_VREQ_GET_USB_SPEED (uint8_t)(0x80)
#define B200_VREQ_GET_STATUS (uint8_t)(0x83)
#define B200_VREQ_AD9361_CTRL_WRITE (uint8_t)(0x90)
#define B200_VREQ_AD9361_CTRL_READ (uint8_t)(0x91)
#define B200_VREQ_AD9361_LOOPBACK (uint8_t)(0x92)
#define B200_VREQ_RESET_DEVICE (uint8_t)(0x99)
#define B200_VREQ_EEPROM_WRITE (uint8_t)(0xBA)
#define B200_VREQ_EEPROM_READ (uint8_t)(0xBB)
#define EVENT_BITSTREAM_START (1 << 1)
#define EVENT_GPIO_DONE_HIGH (1 << 2)
#define EVENT_GPIO_INITB_RISE (1 << 3)
#define EVENT_FPGA_CONFIG (1 << 4)
#define EVENT_RE_ENUM (1 << 5)
#define EVENT_AD9361_XACT_INIT (1 << 6)
#define EVENT_AD9361_XACT_DONE (1 << 7)
/* FX3 States */
#define STATE_UNDEFINED (0)
#define STATE_FPGA_READY (1)
#define STATE_CONFIGURING_FPGA (2)
#define STATE_BUSY (3)
#define STATE_RUNNING (4)
#define STATE_UNCONFIGURED (5)
#define STATE_ERROR (6)
/* Define the USB endpoints, sockets, and directions. The LSB is the socket
* number, and the MSB is the direction. For USB 2.0, sockets are mapped
* one-to-one since they must be uni-directional. */
#define VREQ_ENDPOINT_PRODUCER 0x00 // OUT (host -> FX3)
#define VREQ_ENDPOINT_CONSUMER 0x80 // IN (FX3 -> host)
#define DATA_ENDPOINT_PRODUCER 0x02 // OUT (host -> FX3), produces for FPGA
#define DATA_ENDPOINT_CONSUMER 0x86 // IN (FX3 -> host), consumes from FPGA
#define CTRL_ENDPOINT_PRODUCER 0x04 // OUT (host -> FX3), produces for FPGA
#define CTRL_ENDPOINT_CONSUMER 0x88 // IN (FX3 -> host), consumes from FPGA
#define PRODUCER_DATA_SOCKET CY_U3P_UIB_SOCKET_PROD_2
#define CONSUMER_DATA_SOCKET CY_U3P_UIB_SOCKET_CONS_6
#define PRODUCER_CTRL_SOCKET CY_U3P_UIB_SOCKET_PROD_4
#define CONSUMER_CTRL_SOCKET CY_U3P_UIB_SOCKET_CONS_8
#define DATA_TX_PPORT_SOCKET CY_U3P_PIB_SOCKET_0
#define DATA_RX_PPORT_SOCKET CY_U3P_PIB_SOCKET_1
#define CTRL_COMM_PPORT_SOCKET CY_U3P_PIB_SOCKET_2
#define CTRL_RESP_PPORT_SOCKET CY_U3P_PIB_SOCKET_3
/* Descriptor definitions for USB enumerations. */
extern uint8_t b200_usb2_dev_desc[];
extern uint8_t b200_usb3_dev_desc[];
extern const uint8_t b200_dev_qual_desc[];
extern const uint8_t b200_usb_fs_config_desc[];
extern const uint8_t b200_usb_hs_config_desc[];
extern const uint8_t b200_usb_bos_desc[];
extern const uint8_t b200_usb_ss_config_desc[];
extern const uint8_t b200_string_lang_id_desc[];
extern const uint8_t b200_usb_manufacture_desc[];
extern const uint8_t b200_usb_product_desc[];
extern uint8_t dev_serial[];
#include "cyu3externcend.h"
#endif /* _B200_MAIN_H */

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//
// Copyright 2013-2014 Ettus Research LLC
//
/* Define the USB 2.0 and USB 3.0 enumeration descriptions for the USRP B200
* device. */
#include "b200_main.h"
/* Standard Device Descriptor for USB 2.0 */
uint8_t b200_usb2_dev_desc[] __attribute__ ((aligned (32))) =
{
0x12, /* Descriptor size */
CY_U3P_USB_DEVICE_DESCR, /* Device descriptor type */
0x10,0x02, /* USB 2.10 */
0xFF, /* Device class */
0x00, /* Device sub-class */
0x00, /* Device protocol */
0x40, /* Maxpacket size for EP0 : 64 bytes */
0xB4,0x04, /* Vendor ID */
0xF0,0x00, /* Product ID */
0x00,0x00, /* Device release number */
0x01, /* Manufacture string index */
0x02, /* Product string index */
0x03, /* Serial number string index */
0x01 /* Number of configurations */
};
/* Standard Device Descriptor for USB 3.0 */
uint8_t b200_usb3_dev_desc[] __attribute__ ((aligned (32))) =
{
0x12, /* Descriptor size */
CY_U3P_USB_DEVICE_DESCR, /* Device descriptor type */
0x00,0x03, /* USB 3.0 */
0xFF, /* Device class */
0x00, /* Device sub-class */
0x00, /* Device protocol */
0x09, /* Maxpacket size for EP0 : 2^9 */
0xB4,0x04, /* Vendor ID */
0xF0,0x00, /* Product ID */
0x00,0x00, /* Device release number */
0x01, /* Manufacture string index */
0x02, /* Product string index */
0x03, /* Serial number string index */
0x01 /* Number of configurations */
};
/* Binary Device Object Store Descriptor */
const uint8_t b200_usb_bos_desc[] __attribute__ ((aligned (32))) =
{
0x05, /* Descriptor size */
CY_U3P_BOS_DESCR, /* Device descriptor type */
0x16,0x00, /* Length of this descriptor and all sub descriptors */
0x02, /* Number of device capability descriptors */
/* USB 2.0 extension */
0x07, /* Descriptor size */
CY_U3P_DEVICE_CAPB_DESCR, /* Device capability type descriptor */
CY_U3P_USB2_EXTN_CAPB_TYPE, /* USB 2.0 extension capability type */
0x02,0x00,0x00,0x00, /* Supported device level features: LPM support */
/* SuperSpeed device capability */
0x0A, /* Descriptor size */
CY_U3P_DEVICE_CAPB_DESCR, /* Device capability type descriptor */
CY_U3P_SS_USB_CAPB_TYPE, /* SuperSpeed device capability type */
0x00, /* Supported device level features */
0x0E,0x00, /* Speeds supported by the device : SS, HS and FS */
0x03, /* Functionality support */
0x00, /* U1 Device Exit latency */
0x00,0x00 /* U2 Device Exit latency */
};
/* Standard Device Qualifier Descriptor */
const uint8_t b200_dev_qual_desc[] __attribute__ ((aligned (32))) =
{
0x0A, /* Descriptor size */
CY_U3P_USB_DEVQUAL_DESCR, /* Device qualifier descriptor type */
0x00,0x02, /* USB 2.0 */
0xFF, /* Device class */
0x00, /* Device sub-class */
0x00, /* Device protocol */
0x40, /* Maxpacket size for EP0 : 64 bytes */
0x01, /* Number of configurations */
0x00 /* Reserved */
};
/* Standard Full Speed Configuration Descriptor */
const uint8_t b200_usb_fs_config_desc[] __attribute__ ((aligned (32))) =
{
/* Configuration descriptor */
0x09, /* Descriptor size */
CY_U3P_USB_CONFIG_DESCR, /* Configuration descriptor type */
0x52,0x00, /* Length of this descriptor and all sub descriptors */
0x05, /* Number of interfaces */
0x01, /* Configuration number */
0x00, /* Configuration string index */
0x80, /* Config characteristics - bus powered */
0x01, /* Lie about the max power consumption (in 2mA unit) : 2mA */
/* Interface descriptor */
0x09, /* Descriptor size */
CY_U3P_USB_INTRFC_DESCR, /* Interface descriptor type */
0x00, /* Interface number */
0x00, /* Alternate setting number */
0x00, /* Number of endpoints */
0xFF, /* Interface class */
0x00, /* Interface sub class */
0x00, /* Interface protocol code */
0x02, /* Interface descriptor string index */
/* Interface descriptor */
0x09, /* Descriptor size */
CY_U3P_USB_INTRFC_DESCR, /* Interface descriptor type */
0x01, /* Interface number */
0x00, /* Alternate setting number */
0x01, /* Number of endpoints */
0xFF, /* Interface class */
0x00, /* Interface sub class */
0x00, /* Interface protocol code */
0x02, /* Interface descriptor string index */
/* Endpoint descriptor for producer EP */
0x07, /* Descriptor size */
CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */
DATA_ENDPOINT_PRODUCER, /* Endpoint address and description */
CY_U3P_USB_EP_BULK, /* Bulk endpoint type */
0x40,0x00, /* Max packet size = 64 bytes */
0x00, /* Servicing interval for data transfers : 0 for bulk */
/* Interface descriptor */
0x09, /* Descriptor size */
CY_U3P_USB_INTRFC_DESCR, /* Interface descriptor type */
0x02, /* Interface number */
0x00, /* Alternate setting number */
0x01, /* Number of endpoints */
0xFF, /* Interface class */
0x00, /* Interface sub class */
0x00, /* Interface protocol code */
0x02, /* Interface descriptor string index */
/* Endpoint descriptor for consumer EP */
0x07, /* Descriptor size */
CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */
DATA_ENDPOINT_CONSUMER, /* Endpoint address and description */
CY_U3P_USB_EP_BULK, /* Bulk endpoint type */
0x40,0x00, /* Max packet size = 64 bytes */
0x00, /* Servicing interval for data transfers : 0 for bulk */
/* Interface descriptor */
0x09, /* Descriptor size */
CY_U3P_USB_INTRFC_DESCR, /* Interface descriptor type */
0x03, /* Interface number */
0x00, /* Alternate setting number */
0x01, /* Number of endpoints */
0xFF, /* Interface class */
0x00, /* Interface sub class */
0x00, /* Interface protocol code */
0x02, /* Interface descriptor string index */
/* Endpoint descriptor for producer EP */
0x07, /* Descriptor size */
CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */
CTRL_ENDPOINT_PRODUCER, /* Endpoint address and description */
CY_U3P_USB_EP_BULK, /* Bulk endpoint type */
0x40,0x00, /* Max packet size = 64 bytes */
0x00, /* Servicing interval for data transfers : 0 for bulk */
/* Interface descriptor */
0x09, /* Descriptor size */
CY_U3P_USB_INTRFC_DESCR, /* Interface descriptor type */
0x04, /* Interface number */
0x00, /* Alternate setting number */
0x01, /* Number of endpoints */
0xFF, /* Interface class */
0x00, /* Interface sub class */
0x00, /* Interface protocol code */
0x02, /* Interface descriptor string index */
/* Endpoint descriptor for consumer EP */
0x07, /* Descriptor size */
CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */
CTRL_ENDPOINT_CONSUMER, /* Endpoint address and description */
CY_U3P_USB_EP_BULK, /* Bulk endpoint type */
0x40,0x00, /* Max packet size = 64 bytes */
0x00 /* Servicing interval for data transfers : 0 for bulk */
};
/* Standard High Speed Configuration Descriptor */
const uint8_t b200_usb_hs_config_desc[] __attribute__ ((aligned (32))) =
{
/* Configuration descriptor */
0x09, /* Descriptor size */
CY_U3P_USB_CONFIG_DESCR, /* Configuration descriptor type */
0x52,0x00, /* Length of this descriptor and all sub descriptors */
0x05, /* Number of interfaces */
0x01, /* Configuration number */
0x00, /* COnfiguration string index */
0x80, /* Config characteristics - bus powered */
0x01, /* Lie about the max power consumption (in 2mA unit) : 2mA */
/* Interface descriptor */
0x09, /* Descriptor size */
CY_U3P_USB_INTRFC_DESCR, /* Interface Descriptor type */
0x00, /* Interface number */
0x00, /* Alternate setting number */
0x00, /* Number of endpoints */
0xFF, /* Interface class */
0x00, /* Interface sub class */
0x00, /* Interface protocol code */
0x02, /* Interface descriptor string index */
/* Interface descriptor */
0x09, /* Descriptor size */
CY_U3P_USB_INTRFC_DESCR, /* Interface Descriptor type */
0x01, /* Interface number */
0x00, /* Alternate setting number */
0x01, /* Number of endpoints */
0xFF, /* Interface class */
0x00, /* Interface sub class */
0x00, /* Interface protocol code */
0x02, /* Interface descriptor string index */
/* Endpoint descriptor for producer EP */
0x07, /* Descriptor size */
CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */
DATA_ENDPOINT_PRODUCER, /* Endpoint address and description */
CY_U3P_USB_EP_BULK, /* Bulk endpoint type */
0x00,0x02, /* Max packet size = 512 bytes */
0x00, /* Servicing interval for data transfers : 0 for bulk */
/* Interface descriptor */
0x09, /* Descriptor size */
CY_U3P_USB_INTRFC_DESCR, /* Interface Descriptor type */
0x02, /* Interface number */
0x00, /* Alternate setting number */
0x01, /* Number of endpoints */
0xFF, /* Interface class */
0x00, /* Interface sub class */
0x00, /* Interface protocol code */
0x02, /* Interface descriptor string index */
/* Endpoint descriptor for consumer EP */
0x07, /* Descriptor size */
CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */
DATA_ENDPOINT_CONSUMER, /* Endpoint address and description */
CY_U3P_USB_EP_BULK, /* Bulk endpoint type */
0x00,0x02, /* Max packet size = 512 bytes */
0x00, /* Servicing interval for data transfers : 0 for bulk */
/* Interface descriptor */
0x09, /* Descriptor size */
CY_U3P_USB_INTRFC_DESCR, /* Interface Descriptor type */
0x03, /* Interface number */
0x00, /* Alternate setting number */
0x01, /* Number of endpoints */
0xFF, /* Interface class */
0x00, /* Interface sub class */
0x00, /* Interface protocol code */
0x02, /* Interface descriptor string index */
/* Endpoint descriptor for producer EP */
0x07, /* Descriptor size */
CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */
CTRL_ENDPOINT_PRODUCER, /* Endpoint address and description */
CY_U3P_USB_EP_BULK, /* Bulk endpoint type */
0x00,0x02, /* Max packet size = 512 bytes */
0x00, /* Servicing interval for data transfers : 0 for bulk */
/* Interface descriptor */
0x09, /* Descriptor size */
CY_U3P_USB_INTRFC_DESCR, /* Interface Descriptor type */
0x04, /* Interface number */
0x00, /* Alternate setting number */
0x01, /* Number of endpoints */
0xFF, /* Interface class */
0x00, /* Interface sub class */
0x00, /* Interface protocol code */
0x02, /* Interface descriptor string index */
/* Endpoint descriptor for consumer EP */
0x07, /* Descriptor size */
CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */
CTRL_ENDPOINT_CONSUMER, /* Endpoint address and description */
CY_U3P_USB_EP_BULK, /* Bulk endpoint type */
0x00,0x02, /* Max packet size = 512 bytes */
0x00 /* Servicing interval for data transfers : 0 for bulk */
};
/* Standard Super Speed Configuration Descriptor */
const uint8_t b200_usb_ss_config_desc[] __attribute__ ((aligned (32))) =
{
/* Configuration descriptor */
0x09, /* Descriptor size */
CY_U3P_USB_CONFIG_DESCR, /* Configuration descriptor type */
0x6A,0x00, /* Length of this descriptor and all sub descriptors */
0x05, /* Number of interfaces */
0x01, /* Configuration number */
0x00, /* COnfiguration string index */
0x80, /* Config characteristics - D6: Self power; D5: Remote wakeup */
0x01, /* Lie about the max power consumption (in 8mA unit) : 8mA */
/* Interface descriptor */
0x09, /* Descriptor size */
CY_U3P_USB_INTRFC_DESCR, /* Interface Descriptor type */
0x00, /* Interface number */
0x00, /* Alternate setting number */
0x00, /* Number of end points */
0xFF, /* Interface class */
0x00, /* Interface sub class */
0x00, /* Interface protocol code */
0x02, /* Interface descriptor string index */
/* Interface descriptor */
0x09, /* Descriptor size */
CY_U3P_USB_INTRFC_DESCR, /* Interface Descriptor type */
0x01, /* Interface number */
0x00, /* Alternate setting number */
0x01, /* Number of end points */
0xFF, /* Interface class */
0x00, /* Interface sub class */
0x00, /* Interface protocol code */
0x02, /* Interface descriptor string index */
/* Endpoint descriptor for producer EP */
0x07, /* Descriptor size */
CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */
DATA_ENDPOINT_PRODUCER, /* Endpoint address and description */
CY_U3P_USB_EP_BULK, /* Bulk endpoint type */
0x00,0x04, /* Max packet size = 1024 bytes */
0x00, /* Servicing interval for data transfers : 0 for bulk */
/* Super speed endpoint companion descriptor for producer EP */
0x06, /* Descriptor size */
CY_U3P_SS_EP_COMPN_DESCR, /* SS endpoint companion descriptor type */
(USB3_PACKETS_PER_BURST - 1), /* Max no. of packets in a burst : 0: burst 1 packet at a time */
0x00, /* Max streams for bulk EP = 0 (No streams) */
0x00,0x00, /* Service interval for the EP : 0 for bulk */
/* Interface descriptor */
0x09, /* Descriptor size */
CY_U3P_USB_INTRFC_DESCR, /* Interface Descriptor type */
0x02, /* Interface number */
0x00, /* Alternate setting number */
0x01, /* Number of end points */
0xFF, /* Interface class */
0x00, /* Interface sub class */
0x00, /* Interface protocol code */
0x02, /* Interface descriptor string index */
/* Endpoint descriptor for consumer EP */
0x07, /* Descriptor size */
CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */
DATA_ENDPOINT_CONSUMER, /* Endpoint address and description */
CY_U3P_USB_EP_BULK, /* Bulk endpoint type */
0x00,0x04, /* Max packet size = 1024 bytes */
0x00, /* Servicing interval for data transfers : 0 for Bulk */
/* Super speed endpoint companion descriptor for consumer EP */
0x06, /* Descriptor size */
CY_U3P_SS_EP_COMPN_DESCR, /* SS endpoint companion descriptor type */
(USB3_PACKETS_PER_BURST - 1), /* Max no. of packets in a burst : 0: burst 1 packet at a time */
0x00, /* Max streams for bulk EP = 0 (No streams) */
0x00,0x00, /* Service interval for the EP : 0 for bulk */
/* Interface descriptor */
0x09, /* Descriptor size */
CY_U3P_USB_INTRFC_DESCR, /* Interface Descriptor type */
0x03, /* Interface number */
0x00, /* Alternate setting number */
0x01, /* Number of end points */
0xFF, /* Interface class */
0x00, /* Interface sub class */
0x00, /* Interface protocol code */
0x02, /* Interface descriptor string index */
/* Endpoint descriptor for producer EP */
0x07, /* Descriptor size */
CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */
CTRL_ENDPOINT_PRODUCER, /* Endpoint address and description */
CY_U3P_USB_EP_BULK, /* Bulk endpoint type */
0x00,0x04, /* Max packet size = 1024 bytes */
0x00, /* Servicing interval for data transfers : 0 for bulk */
/* Super speed endpoint companion descriptor for producer EP */
0x06, /* Descriptor size */
CY_U3P_SS_EP_COMPN_DESCR, /* SS endpoint companion descriptor type */
(USB3_PACKETS_PER_BURST - 1), /* Max no. of packets in a burst : 0: burst 1 packet at a time */
0x00, /* Max streams for bulk EP = 0 (No streams) */
0x00,0x00, /* Service interval for the EP : 0 for bulk */
/* Interface descriptor */
0x09, /* Descriptor size */
CY_U3P_USB_INTRFC_DESCR, /* Interface Descriptor type */
0x04, /* Interface number */
0x00, /* Alternate setting number */
0x01, /* Number of end points */
0xFF, /* Interface class */
0x00, /* Interface sub class */
0x00, /* Interface protocol code */
0x02, /* Interface descriptor string index */
/* Endpoint descriptor for consumer EP */
0x07, /* Descriptor size */
CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */
CTRL_ENDPOINT_CONSUMER, /* Endpoint address and description */
CY_U3P_USB_EP_BULK, /* Bulk endpoint type */
0x00,0x04, /* Max packet size = 1024 bytes */
0x00, /* Servicing interval for data transfers : 0 for Bulk */
/* Super speed endpoint companion descriptor for consumer EP */
0x06, /* Descriptor size */
CY_U3P_SS_EP_COMPN_DESCR, /* SS endpoint companion descriptor type */
(USB3_PACKETS_PER_BURST - 1), /* Max no. of packets in a burst : 0: burst 1 packet at a time */
0x00, /* Max streams for bulk EP = 0 (No streams) */
0x00,0x00 /* Service interval for the EP : 0 for bulk */
};
/* Standard Language ID String Descriptor */
const uint8_t b200_string_lang_id_desc[] __attribute__ ((aligned (32))) =
{
0x04, /* Descriptor Size */
CY_U3P_USB_STRING_DESCR, /* Device Descriptor Type */
0x09,0x04 /* Language ID supported */
};
/* Standard Manufacturer String Descriptor */
const uint8_t b200_usb_manufacture_desc[] __attribute__ ((aligned (32))) =
{
0x26, /* Descriptor Size */
CY_U3P_USB_STRING_DESCR, /* Device Descriptor Type */
'E',0x00,
't',0x00,
't',0x00,
'u',0x00,
's',0x00,
' ',0x00,
'R',0x00,
'e',0x00,
's',0x00,
'e',0x00,
'a',0x00,
'r',0x00,
'c',0x00,
'h',0x00,
' ',0x00,
'L',0x00,
'L',0x00,
'C',0x00
};
/* Standard Product String Descriptor */
const uint8_t b200_usb_product_desc[] __attribute__ ((aligned (32))) =
{
0x14, /* Descriptor Size */
CY_U3P_USB_STRING_DESCR, /* Device Descriptor Type */
'U',0x00,
'S',0x00,
'R',0x00,
'P',0x00,
' ',0x00,
'B',0x00,
'2',0x00,
'0',0x00,
'0',0x00
};
/* Microsoft OS Descriptor. */
const uint8_t CyFxUsbOSDscr[] __attribute__ ((aligned (32))) =
{
0x10,
CY_U3P_USB_STRING_DESCR,
'O', 0x00,
'S', 0x00,
' ', 0x00,
'D', 0x00,
'e', 0x00,
's', 0x00,
'c', 0x00
};
uint8_t dev_serial[20] __attribute__ ((aligned (32))) =
{
0x14,
CY_U3P_USB_STRING_DESCR,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00
};
/* Place this buffer as the last buffer so that no other variable / code shares
* the same cache line. Do not add any other variables / arrays in this file.
* This will lead to variables sharing the same cache line. */
const uint8_t CyFxUsbDscrAlignBuffer[32] __attribute__ ((aligned (32)));

21
firmware/fx3/b200/b200_vrq.h Normal file
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@ -0,0 +1,21 @@
//
// Copyright 2013-2014 Ettus Research LLC
//
/* This file defines b200 vendor requests handlers, version 1
*/
#ifndef B200_VRQ_H
#define B200_VRQ_H
uint32_t ad9361_transact_spi(const uint32_t bits);
// note: for a write instruction bit 7 from byte 0 is set to 1
#define MAKE_AD9361_WRITE(dest, reg, val) {dest[0] = 0x80 | ((reg >> 8) & 0x3F); \
dest[1] = reg & 0xFF; \
dest[2] = val;}
#define MAKE_AD9361_READ(dest, reg) {dest[0] = (reg >> 8) & 0x3F; \
dest[1] = reg & 0xFF;}
#endif //B200_VRQ_H

68
firmware/fx3/b200/fx3_mem_map.patch Normal file
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@ -0,0 +1,68 @@
diff -ur 1.2.3-orig/common/cyfxtx.c 1.2.3/common/cyfxtx.c
--- 1.2.3-orig/common/cyfxtx.c 2013-02-07 17:16:54.000000000 -0800
+++ 1.2.3/common/cyfxtx.c 2014-03-25 16:56:12.484602382 -0700
@@ -33,7 +33,7 @@
such as thread stacks and memory for message queues. The Cypress FX3
libraries require a Mem heap size of at least 32 KB.
*/
-#define CY_U3P_MEM_HEAP_BASE ((uint8_t *)0x40038000)
+#define CY_U3P_MEM_HEAP_BASE ((uint8_t *)0x40044000)
#define CY_U3P_MEM_HEAP_SIZE (0x8000)
/* The last 32 KB of RAM is reserved for 2-stage boot operation. This value can be changed to
diff -ur 1.2.3-orig/common/fx3.ld 1.2.3/common/fx3.ld
--- 1.2.3-orig/common/fx3.ld 2013-02-07 17:16:54.000000000 -0800
+++ 1.2.3/common/fx3.ld 2014-03-25 16:59:40.872240377 -0700
@@ -26,10 +26,11 @@
The default memory map used for FX3 applications is as follows:
Descriptor area Base: 0x40000000 Size: 12KB
- Code area Base: 0x40003000 Size: 180KB
- Data area Base: 0x40030000 Size: 32KB
- Driver heap Base: 0x40038000 Size: 32KB (Update cyfxtx.c to change this.)
- Buffer area Base: 0x40040000 Size: 256KB (Update cyfxtx.c to change this.)
+ Code area Base: 0x40003000 Size: 212KB
+ Data area Base: 0x40038000 Size: 32KB
+ Heap Base: 0x40040000 Size: 16KB
+ Driver heap Base: 0x40044000 Size: 32KB (Update cyfxtx.c to change this.)
+ Buffer area Base: 0x4004C000 Size: 208KB (Update cyfxtx.c to change this.)
Interrupt handlers to be placed in I-TCM (16KB).
The first 256 bytes of ITCM are reserved for Exception Vectors.
@@ -52,8 +53,8 @@
MEMORY
{
I-TCM : ORIGIN = 0x100, LENGTH = 0x3F00
- SYS_MEM : ORIGIN = 0x40003000 LENGTH = 0x2D000
- DATA : ORIGIN = 0x40030000 LENGTH = 0x8000
+ SYS_MEM : ORIGIN = 0x40003000 LENGTH = 0x35000
+ DATA : ORIGIN = 0x40038000 LENGTH = 0x8000
}
SECTIONS
@@ -75,7 +76,7 @@
_etext = .;
} > SYS_MEM
- . = 0x40030000;
+ . = 0x40038000;
.data :
{
_data = .;
@@ -104,5 +105,16 @@
} > DATA
__exidx_end = .;
+ PROVIDE(__exidx_end = __exidx_end);
+
+ . = ALIGN(4);
+ __heap_start = 0x40040000;
+ PROVIDE(__heap_start = __heap_start);
+
+ . = ALIGN(4);
+ __heap_end = 0x40044000;
+ PROVIDE(__heap_end = __heap_end);
+
+ PROVIDE(__heap_size = __heap_end - __heap_start);
}

55
firmware/fx3/b200/makefile Normal file
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#
# Copyright 2013-2014 Ettus Research LLC
#
HEX_OUT = usrp_b200_fw.hex
all:$(HEX_OUT)
# Pull in the Cypress SDK files to build the firmware
FX3FWROOT=..
FX3PFWROOT=../u3p_firmware
include $(FX3FWROOT)/common/fx3_build_config.mak
ifndef OC
OC = arm-none-eabi-objcopy
endif
MODULE = b200_main
SOURCE += $(MODULE).c
SOURCE += b200_usb_descriptors.c
SOURCE += b200_ad9361.c
SOURCE += b200_i2c.c
INCLUDES = b200_main.h b200_vrq.h b200_gpifconfig.h b200_i2c.h
INCLUDES += ../ad9361/include/ad9361_transaction.h
INCFLAGS = -I ../ad9361/include
LDLIBS += \
"$$ARMGCC_INSTALL_PATH"/arm-none-eabi/lib/libm.a
C_OBJECT=$(SOURCE:%.c=./%.o)
A_OBJECT=$(SOURCE_ASM:%.S=./%.o)
EXES = $(MODULE).$(EXEEXT)
$(MODULE).$(EXEEXT): $(A_OBJECT) $(C_OBJECT)
$(LINK) $(LINKFLAGS)
$(C_OBJECT) : %.o : %.c $(INCLUDES)
$(COMPILE) $(INCFLAGS)
$(A_OBJECT) : %.o : %.S
$(ASSEMBLE)
clean:
rm -f ./$(MODULE).$(EXEEXT)
rm -f ./$(MODULE).map
rm -f ./*.o
$(HEX_OUT): $(C_OBJECT) $(A_OBJECT) $(EXES)
$(OC) -O ihex $(EXES) $@
#[]#

30
firmware/fx3/gpif2_designer/b200_v2.cydsn/b200_v2.cyfx Normal file
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<?xml version="1.0" encoding="us-ascii"?>
<CyXmlSerializer>
<!--This file is machine generated and read. It is not intended to be edited by hand.-->
<!--Due to this, there is no schema for this file.-->
<CyGuid_7d237aff-d944-11da-aaba-00164119d63b type_name="CyGpif2Designer.Common.PrjMgmt.Model.CyPrjMgmtGpif2exe" version="2">
<CyGuid_7d237b00-d944-11da-aaba-00164119d63b type_name="CyGpif2Designer.Common.PrjMgmt.Model.CyPrjMgmtProject" version="1">
<ProjectDocs>
<CyGuid_7d237b03-d944-11da-aaba-00164119d63b type_name="CyGpif2Designer.Common.PrjMgmt.Model.CyPrjMgmtItem" name="gpif2model.xml" persistent="./projectfiles/gpif2model.xml" target="7d237b02-d944-11da-aaba-00164119d63b">
<Hidden v="False" />
</CyGuid_7d237b03-d944-11da-aaba-00164119d63b>
<CyGuid_7d237b03-d944-11da-aaba-00164119d63b type_name="CyGpif2Designer.Common.PrjMgmt.Model.CyPrjMgmtItem" name="gpif2view.xml" persistent="./projectfiles/gpif2view.xml" target="7d237b01-d944-11da-aaba-00164119d63b">
<Hidden v="False" />
</CyGuid_7d237b03-d944-11da-aaba-00164119d63b>
<CyGuid_7d237b03-d944-11da-aaba-00164119d63b type_name="CyGpif2Designer.Common.PrjMgmt.Model.CyPrjMgmtItem" name="gpif2timingsimulation.xml" persistent="./projectfiles/gpif2timingsimulation.xml" target="3ad448c6-d155-4f76-a7fb-e760cd8e6feb">
<Hidden v="False" />
</CyGuid_7d237b03-d944-11da-aaba-00164119d63b>
</ProjectDocs>
<OutputDocs>
<CyGuid_7d237b03-d944-11da-aaba-00164119d63b type_name="CyGpif2Designer.Common.PrjMgmt.Model.CyPrjMgmtItem" name="cyfxgpif2config.h" persistent="C:\Users\bhilburn\Documents\GPIF II Designer\b200_v2.cydsn\cyfxgpif2config.h" target="7d237afd-d944-11da-aaba-00164119d63b">
<Hidden v="False" />
</CyGuid_7d237b03-d944-11da-aaba-00164119d63b>
</OutputDocs>
</CyGuid_7d237b00-d944-11da-aaba-00164119d63b>
<Settings>
<Setting name="GPIF2_OutputName" value="cyfxgpif2config" />
<Setting name="GPIF2_OutputLocation" value="C:\Users\bhilburn\Documents\GPIF II Designer\b200_v2.cydsn" />
<Setting name="GPIF2_Template" value="C:\Program Files\Cypress\GPIFII Designer\inputs\outputtemplates\cygpif2cheadertemplate.tpl" />
</Settings>
</CyGuid_7d237aff-d944-11da-aaba-00164119d63b>
</CyXmlSerializer>

174
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/*
* Project Name: b200_v2.cyfx
* Time : 10/23/2013 12:03:48
* Device Type: FX3
* Project Type: GPIF2
*
*
*
*
* This is a generated file and should not be modified
* This file need to be included only once in the firmware
* This file is generated by Gpif2 designer tool version - 1.0.715.0
*
*/
#ifndef _INCLUDED_CYFXGPIF2CONFIG_
#define _INCLUDED_CYFXGPIF2CONFIG_
#include "cyu3types.h"
#include "cyu3gpif.h"
/* Summary
Number of states in the state machine
*/
#define CY_NUMBER_OF_STATES 6
/* Summary
Mapping of user defined state names to state indices
*/
#define RESET 0
#define IDLE 1
#define READ 2
#define WRITE 3
#define SHORT_PKT 4
#define ZLP 5
/* Summary
Initial value of early outputs from the state machine.
*/
#define ALPHA_RESET 0x8
/* Summary
Transition function values used in the state machine.
*/
uint16_t CyFxGpifTransition[] = {
0x0000, 0x8080, 0x2222, 0x5555, 0x7F7F, 0x1F1F, 0x8888
};
/* Summary
Table containing the transition information for various states.
This table has to be stored in the WAVEFORM Registers.
This array consists of non-replicated waveform descriptors and acts as a
waveform table.
*/
CyU3PGpifWaveData CyFxGpifWavedata[] = {
{{0x1E086001,0x000100C4,0x80000000},{0x00000000,0x00000000,0x00000000}},
{{0x4E080302,0x00000200,0x80000000},{0x00000000,0x00000000,0x00000000}},
{{0x1E086001,0x000100C4,0x80000000},{0x4E040704,0x20000200,0xC0100000}},
{{0x00000000,0x00000000,0x00000000},{0x00000000,0x00000000,0x00000000}},
{{0x00000000,0x00000000,0x00000000},{0x3E738705,0x00000200,0xC0100000}},
{{0x00000000,0x00000000,0x00000000},{0x5E002703,0x2001020C,0x80000000}},
{{0x00000000,0x00000000,0x00000000},{0x4E040704,0x20000200,0xC0100000}}
};
/* Summary
Table that maps state indices to the descriptor table indices.
*/
uint8_t CyFxGpifWavedataPosition[] = {
0,1,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
0,4,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
0,5,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
0,6,0,2,0,0
};
/* Summary
GPIF II configuration register values.
*/
uint32_t CyFxGpifRegValue[] = {
0x80000380, /* CY_U3P_PIB_GPIF_CONFIG */
0x000010AC, /* CY_U3P_PIB_GPIF_BUS_CONFIG */
0x01070002, /* CY_U3P_PIB_GPIF_BUS_CONFIG2 */
0x00000044, /* CY_U3P_PIB_GPIF_AD_CONFIG */
0x00000000, /* CY_U3P_PIB_GPIF_STATUS */
0x00000000, /* CY_U3P_PIB_GPIF_INTR */
0x00000000, /* CY_U3P_PIB_GPIF_INTR_MASK */
0x00000082, /* CY_U3P_PIB_GPIF_SERIAL_IN_CONFIG */
0x00000782, /* CY_U3P_PIB_GPIF_SERIAL_OUT_CONFIG */
0x00000500, /* CY_U3P_PIB_GPIF_CTRL_BUS_DIRECTION */
0x0000FFCF, /* CY_U3P_PIB_GPIF_CTRL_BUS_DEFAULT */
0x000000BF, /* CY_U3P_PIB_GPIF_CTRL_BUS_POLARITY */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_TOGGLE */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000018, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000019, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
0x00000006, /* CY_U3P_PIB_GPIF_CTRL_COUNT_CONFIG */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COUNT_RESET */
0x0000FFFF, /* CY_U3P_PIB_GPIF_CTRL_COUNT_LIMIT */
0x0000010A, /* CY_U3P_PIB_GPIF_ADDR_COUNT_CONFIG */
0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COUNT_RESET */
0x0000FFFF, /* CY_U3P_PIB_GPIF_ADDR_COUNT_LIMIT */
0x00000000, /* CY_U3P_PIB_GPIF_STATE_COUNT_CONFIG */
0x0000FFFF, /* CY_U3P_PIB_GPIF_STATE_COUNT_LIMIT */
0x0000010A, /* CY_U3P_PIB_GPIF_DATA_COUNT_CONFIG */
0x00000000, /* CY_U3P_PIB_GPIF_DATA_COUNT_RESET */
0x0000FFFF, /* CY_U3P_PIB_GPIF_DATA_COUNT_LIMIT */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COMP_VALUE */
0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COMP_MASK */
0x00000000, /* CY_U3P_PIB_GPIF_DATA_COMP_VALUE */
0x00000000, /* CY_U3P_PIB_GPIF_DATA_COMP_MASK */
0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COMP_VALUE */
0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COMP_MASK */
0x00000000, /* CY_U3P_PIB_GPIF_DATA_CTRL */
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
0x80010400, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
0x80010401, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
0x80010402, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
0x80010403, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
0x00000000, /* CY_U3P_PIB_GPIF_LAMBDA_STAT */
0x00000000, /* CY_U3P_PIB_GPIF_ALPHA_STAT */
0x00000000, /* CY_U3P_PIB_GPIF_BETA_STAT */
0x00080000, /* CY_U3P_PIB_GPIF_WAVEFORM_CTRL_STAT */
0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_SWITCH */
0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_SWITCH_TIMEOUT */
0x00000000, /* CY_U3P_PIB_GPIF_CRC_CONFIG */
0x00000000, /* CY_U3P_PIB_GPIF_CRC_DATA */
0xFFFFFFF1 /* CY_U3P_PIB_GPIF_BETA_DEASSERT */
};
/* Summary
This structure holds all the configuration inputs for the GPIF II.
*/
const CyU3PGpifConfig_t CyFxGpifConfig = {
(uint16_t)(sizeof(CyFxGpifWavedataPosition)/sizeof(uint8_t)),
CyFxGpifWavedata,
CyFxGpifWavedataPosition,
(uint16_t)(sizeof(CyFxGpifTransition)/sizeof(uint16_t)),
CyFxGpifTransition,
(uint16_t)(sizeof(CyFxGpifRegValue)/sizeof(uint32_t)),
CyFxGpifRegValue
};
#endif /* _INCLUDED_CYFXGPIF2CONFIG_ */

140
firmware/fx3/gpif2_designer/b200_v2.cydsn/projectfiles/gpif2model.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<GPIFIIModel version="3">
<InterfaceDefination>
<InterfaceSetting>
<I2SEnabled>False</I2SEnabled>
<I2CEnabled>False</I2CEnabled>
<SPIEnabled>False</SPIEnabled>
<I2SEnabled>False</I2SEnabled>
<ADMuxedEnabled>False</ADMuxedEnabled>
<InterfaceType>Slave</InterfaceType>
<CommunicationType>Synchronous</CommunicationType>
<ClockSource>External</ClockSource>
<ClockEdge>Positive</ClockEdge>
<Endianness>LittleEndian</Endianness>
<DataBusWidth>Bit32</DataBusWidth>
<AddressBuswidth>2</AddressBuswidth>
</InterfaceSetting>
</InterfaceDefination>
<Signals>
<Signal ElementId="INPUT0" SignalType="Input" SpecialFunction="OE">
<DisplayName>SLOE</DisplayName>
<GPIOPinNumber>GPIO_19</GPIOPinNumber>
<Polarity>ActiveLow</Polarity>
</Signal>
<Signal ElementId="INPUT1" SignalType="Input" SpecialFunction="None">
<DisplayName>SLCS</DisplayName>
<GPIOPinNumber>GPIO_17</GPIOPinNumber>
<Polarity>ActiveLow</Polarity>
</Signal>
<Signal ElementId="INPUT2" SignalType="Input" SpecialFunction="None">
<DisplayName>SLWR</DisplayName>
<GPIOPinNumber>GPIO_18</GPIOPinNumber>
<Polarity>ActiveLow</Polarity>
</Signal>
<Signal ElementId="INPUT3" SignalType="Input" SpecialFunction="None">
<DisplayName>SLRD</DisplayName>
<GPIOPinNumber>GPIO_20</GPIOPinNumber>
<Polarity>ActiveLow</Polarity>
</Signal>
<Signal ElementId="INPUT4" SignalType="Input" SpecialFunction="None">
<DisplayName>PKEND</DisplayName>
<GPIOPinNumber>GPIO_24</GPIOPinNumber>
<Polarity>ActiveLow</Polarity>
</Signal>
<Signal ElementId="FLAG0" SignalType="Flags" SpecialFunction="None">
<DisplayName>FLAG0</DisplayName>
<GPIOPinNumber>GPIO_21</GPIOPinNumber>
<IntialValue>Low</IntialValue>
<Polarity>ActiveLow</Polarity>
<Flags>Current_Thread_DMA_Ready</Flags>
</Signal>
<Signal ElementId="FLAG1" SignalType="Flags" SpecialFunction="None">
<DisplayName>FLAG1</DisplayName>
<GPIOPinNumber>GPIO_22</GPIOPinNumber>
<IntialValue>Low</IntialValue>
<Polarity>ActiveLow</Polarity>
<Flags>Current_Thread_DMA_WaterMark</Flags>
</Signal>
</Signals>
<StateMachine>
<AddressCounter />
<DataCounter />
<ControlCounter />
<AddressComparator />
<DataComparator />
<ControlComparator />
<DRQ />
<AddrData />
<State ElementId="STARTSTATE1" StateType="StartState">
<DisplayName>RESET</DisplayName>
<RepeatUntillNextTransition>True</RepeatUntillNextTransition>
<RepeatCount>0</RepeatCount>
</State>
<State ElementId="STATE1" StateType="NormalState">
<DisplayName>IDLE</DisplayName>
<RepeatUntillNextTransition>True</RepeatUntillNextTransition>
<RepeatCount>0</RepeatCount>
<Action ElementId="IN_ADDR0" ActionType="IN_ADDR">
<SampleAddressType>ThreadSelection</SampleAddressType>
<A7Override>DMAAccessAndRegisterAccess</A7Override>
</Action>
</State>
<State ElementId="STATE2" StateType="NormalState">
<DisplayName>READ</DisplayName>
<RepeatUntillNextTransition>True</RepeatUntillNextTransition>
<RepeatCount>0</RepeatCount>
<Action ElementId="DR_DATA0" ActionType="DR_DATA">
<IsDataCounterConnected>False</IsDataCounterConnected>
<DataSourceSink>Socket</DataSourceSink>
<ThreadNumber>Thread0</ThreadNumber>
<SyncBurstMode>Enable</SyncBurstMode>
<DriveNewData>DriveNewData</DriveNewData>
<UpdateSource>True</UpdateSource>
</Action>
</State>
<State ElementId="STATE3" StateType="NormalState">
<DisplayName>WRITE</DisplayName>
<RepeatUntillNextTransition>True</RepeatUntillNextTransition>
<RepeatCount>0</RepeatCount>
<Action ElementId="IN_DATA0" ActionType="IN_DATA">
<DataSourceSink>Socket</DataSourceSink>
<ThreadNumber>Thread0</ThreadNumber>
<SampleData>True</SampleData>
<WriteDataIntoDataSink>True</WriteDataIntoDataSink>
</Action>
</State>
<State ElementId="STATE4" StateType="NormalState">
<DisplayName>SHORT_PKT</DisplayName>
<RepeatUntillNextTransition>False</RepeatUntillNextTransition>
<RepeatCount>0</RepeatCount>
<Action ElementId="COMMIT0" ActionType="COMMIT">
<ThreadNumber>Thread0</ThreadNumber>
</Action>
<Action ElementId="IN_DATA0" ActionType="IN_DATA">
<DataSourceSink>Socket</DataSourceSink>
<ThreadNumber>Thread0</ThreadNumber>
<SampleData>True</SampleData>
<WriteDataIntoDataSink>True</WriteDataIntoDataSink>
</Action>
</State>
<State ElementId="STATE5" StateType="NormalState">
<DisplayName>ZLP</DisplayName>
<RepeatUntillNextTransition>False</RepeatUntillNextTransition>
<RepeatCount>0</RepeatCount>
<Action ElementId="COMMIT0" ActionType="COMMIT">
<ThreadNumber>Thread0</ThreadNumber>
</Action>
</State>
<Transition ElementId="TRANSITION1" SourceState="STARTSTATE1" DestinationState="STATE1" Equation="LOGIC_ONE" />
<Transition ElementId="TRANSITION2" SourceState="STATE1" DestinationState="STATE2" Equation="SLWR&amp;!SLCS&amp;PKEND&amp;!SLRD&amp;!SLOE" />
<Transition ElementId="TRANSITION3" SourceState="STATE1" DestinationState="STATE3" Equation="!SLWR&amp;!SLCS&amp;PKEND&amp;SLRD" />
<Transition ElementId="TRANSITION4" SourceState="STATE1" DestinationState="STATE4" Equation="!SLWR&amp;!SLCS&amp;!PKEND&amp;SLRD" />
<Transition ElementId="TRANSITION5" SourceState="STATE1" DestinationState="STATE5" Equation="SLWR&amp;!SLCS&amp;!PKEND&amp;SLRD" />
<Transition ElementId="TRANSITION6" SourceState="STATE5" DestinationState="STATE1" Equation="PKEND" />
<Transition ElementId="TRANSITION7" SourceState="STATE2" DestinationState="STATE1" Equation="SLRD|SLCS|SLOE" />
<Transition ElementId="TRANSITION8" SourceState="STATE3" DestinationState="STATE1" Equation="(PKEND&amp;SLWR)|SLCS" />
<Transition ElementId="TRANSITION9" SourceState="STATE3" DestinationState="STATE4" Equation="!SLWR&amp;!PKEND" />
<Transition ElementId="TRANSITION10" SourceState="STATE4" DestinationState="STATE1" Equation="PKEND|SLCS|SLWR" />
</StateMachine>
</GPIFIIModel>

49
firmware/fx3/gpif2_designer/b200_v2.cydsn/projectfiles/gpif2timingsimulation.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<GPIFIITimingSimulation version="1">
<Clock>100</Clock>
<BufferSize>512</BufferSize>
<WaterMark>0</WaterMark>
<Scenario Name="Read" CurrentThread="Thread0">
<State StateId="STARTSTATE1" WaitNumber="0" />
<State StateId="STATE1" WaitNumber="0" />
<State StateId="STATE2" WaitNumber="0" />
<State StateId="STATE1" WaitNumber="0" />
</Scenario>
<Scenario Name="Write" CurrentThread="Thread0">
<State StateId="STARTSTATE1" WaitNumber="0" />
<State StateId="STATE1" WaitNumber="0" />
<State StateId="STATE3" WaitNumber="0" />
<State StateId="STATE1" WaitNumber="0" />
</Scenario>
<Scenario Name="BurstRead" CurrentThread="Thread0">
<State StateId="STARTSTATE1" WaitNumber="0" />
<State StateId="STATE1" WaitNumber="0" />
<State StateId="STATE2" WaitNumber="0" />
<State StateId="STATE2" WaitNumber="0" />
<State StateId="STATE2" WaitNumber="0" />
<State StateId="STATE2" WaitNumber="0" />
<State StateId="STATE1" WaitNumber="0" />
</Scenario>
<Scenario Name="BurstWrite" CurrentThread="Thread0">
<State StateId="STARTSTATE1" WaitNumber="0" />
<State StateId="STATE1" WaitNumber="0" />
<State StateId="STATE3" WaitNumber="0" />
<State StateId="STATE3" WaitNumber="0" />
<State StateId="STATE3" WaitNumber="0" />
<State StateId="STATE3" WaitNumber="0" />
<State StateId="STATE3" WaitNumber="0" />
<State StateId="STATE1" WaitNumber="0" />
</Scenario>
<Scenario Name="ShortPkt" CurrentThread="Thread0">
<State StateId="STARTSTATE1" WaitNumber="0" />
<State StateId="STATE1" WaitNumber="0" />
<State StateId="STATE4" WaitNumber="0" />
<State StateId="STATE1" WaitNumber="0" />
</Scenario>
<Scenario Name="ZLP" CurrentThread="Thread0">
<State StateId="STARTSTATE1" WaitNumber="0" />
<State StateId="STATE1" WaitNumber="0" />
<State StateId="STATE5" WaitNumber="0" />
<State StateId="STATE1" WaitNumber="0" />
</Scenario>
</GPIFIITimingSimulation>

183
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<?xml version="1.0" encoding="UTF-8"?>
<Root version="4">
<CyStates>
<CyNormalState>
<Left>363</Left>
<Top>96.4466666666667</Top>
<Width>83</Width>
<Height>70</Height>
<Name>STATE1</Name>
<DisplayName>IDLE</DisplayName>
<zIndex>1</zIndex>
<IsGroup>False</IsGroup>
<ParentID>00000000-0000-0000-0000-000000000000</ParentID>
</CyNormalState>
<CyNormalState>
<Left>237</Left>
<Top>390.446666666667</Top>
<Width>83</Width>
<Height>70</Height>
<Name>STATE2</Name>
<DisplayName>READ</DisplayName>
<zIndex>1</zIndex>
<IsGroup>False</IsGroup>
<ParentID>00000000-0000-0000-0000-000000000000</ParentID>
</CyNormalState>
<CyNormalState>
<Left>551</Left>
<Top>379.446666666667</Top>
<Width>83</Width>
<Height>70</Height>
<Name>STATE3</Name>
<DisplayName>WRITE</DisplayName>
<zIndex>1</zIndex>
<IsGroup>False</IsGroup>
<ParentID>00000000-0000-0000-0000-000000000000</ParentID>
</CyNormalState>
<CyNormalState>
<Left>773</Left>
<Top>233.446666666667</Top>
<Width>83</Width>
<Height>70</Height>
<Name>STATE4</Name>
<DisplayName>SHORT_PKT</DisplayName>
<zIndex>1</zIndex>
<IsGroup>False</IsGroup>
<ParentID>00000000-0000-0000-0000-000000000000</ParentID>
</CyNormalState>
<CyNormalState>
<Left>11</Left>
<Top>196.446666666667</Top>
<Width>83</Width>
<Height>70</Height>
<Name>STATE5</Name>
<DisplayName>ZLP</DisplayName>
<zIndex>1</zIndex>
<IsGroup>False</IsGroup>
<ParentID>00000000-0000-0000-0000-000000000000</ParentID>
</CyNormalState>
<CyStartState>
<Left>29</Left>
<Top>18.4466666666667</Top>
<Width>83</Width>
<Height>70</Height>
<Name>STARTSTATE1</Name>
<DisplayName>RESET</DisplayName>
<zIndex>1</zIndex>
<IsGroup>False</IsGroup>
<ParentID>00000000-0000-0000-0000-000000000000</ParentID>
</CyStartState>
</CyStates>
<CyTransitions>
<CyTransition>
<Name>TRANSITION1</Name>
<TransitionEquation>LOGIC_ONE</TransitionEquation>
<SourceName>STARTSTATE1</SourceName>
<SinkName>STATE1</SinkName>
<SourceConnectorName>Connector</SourceConnectorName>
<SinkConnectorName>Connector</SinkConnectorName>
<SourceArrowSymbol>None</SourceArrowSymbol>
<SinkArrowSymbol>Arrow</SinkArrowSymbol>
<zIndex>0</zIndex>
</CyTransition>
<CyTransition>
<Name>TRANSITION2</Name>
<TransitionEquation>SLWR&amp;!SLCS&amp;PKEND&amp;!SLRD&amp;!SLOE</TransitionEquation>
<SourceName>STATE1</SourceName>
<SinkName>STATE2</SinkName>
<SourceConnectorName>Connector</SourceConnectorName>
<SinkConnectorName>Connector</SinkConnectorName>
<SourceArrowSymbol>None</SourceArrowSymbol>
<SinkArrowSymbol>Arrow</SinkArrowSymbol>
<zIndex>0</zIndex>
</CyTransition>
<CyTransition>
<Name>TRANSITION3</Name>
<TransitionEquation>!SLWR&amp;!SLCS&amp;PKEND&amp;SLRD</TransitionEquation>
<SourceName>STATE1</SourceName>
<SinkName>STATE3</SinkName>
<SourceConnectorName>Connector</SourceConnectorName>
<SinkConnectorName>Connector</SinkConnectorName>
<SourceArrowSymbol>None</SourceArrowSymbol>
<SinkArrowSymbol>Arrow</SinkArrowSymbol>
<zIndex>0</zIndex>
</CyTransition>
<CyTransition>
<Name>TRANSITION4</Name>
<TransitionEquation>!SLWR&amp;!SLCS&amp;!PKEND&amp;SLRD</TransitionEquation>
<SourceName>STATE1</SourceName>
<SinkName>STATE4</SinkName>
<SourceConnectorName>Connector</SourceConnectorName>
<SinkConnectorName>Connector</SinkConnectorName>
<SourceArrowSymbol>None</SourceArrowSymbol>
<SinkArrowSymbol>Arrow</SinkArrowSymbol>
<zIndex>0</zIndex>
</CyTransition>
<CyTransition>
<Name>TRANSITION5</Name>
<TransitionEquation>SLWR&amp;!SLCS&amp;!PKEND&amp;SLRD</TransitionEquation>
<SourceName>STATE1</SourceName>
<SinkName>STATE5</SinkName>
<SourceConnectorName>Connector</SourceConnectorName>
<SinkConnectorName>Connector</SinkConnectorName>
<SourceArrowSymbol>None</SourceArrowSymbol>
<SinkArrowSymbol>Arrow</SinkArrowSymbol>
<zIndex>0</zIndex>
</CyTransition>
<CyTransition>
<Name>TRANSITION6</Name>
<TransitionEquation>PKEND</TransitionEquation>
<SourceName>STATE5</SourceName>
<SinkName>STATE1</SinkName>
<SourceConnectorName>Connector</SourceConnectorName>
<SinkConnectorName>Connector</SinkConnectorName>
<SourceArrowSymbol>None</SourceArrowSymbol>
<SinkArrowSymbol>Arrow</SinkArrowSymbol>
<zIndex>0</zIndex>
</CyTransition>
<CyTransition>
<Name>TRANSITION7</Name>
<TransitionEquation>SLRD|SLCS|SLOE</TransitionEquation>
<SourceName>STATE2</SourceName>
<SinkName>STATE1</SinkName>
<SourceConnectorName>Connector</SourceConnectorName>
<SinkConnectorName>Connector</SinkConnectorName>
<SourceArrowSymbol>None</SourceArrowSymbol>
<SinkArrowSymbol>Arrow</SinkArrowSymbol>
<zIndex>0</zIndex>
</CyTransition>
<CyTransition>
<Name>TRANSITION8</Name>
<TransitionEquation>(PKEND&amp;SLWR)|SLCS</TransitionEquation>
<SourceName>STATE3</SourceName>
<SinkName>STATE1</SinkName>
<SourceConnectorName>Connector</SourceConnectorName>
<SinkConnectorName>Connector</SinkConnectorName>
<SourceArrowSymbol>None</SourceArrowSymbol>
<SinkArrowSymbol>Arrow</SinkArrowSymbol>
<zIndex>0</zIndex>
</CyTransition>
<CyTransition>
<Name>TRANSITION9</Name>
<TransitionEquation>!SLWR&amp;!PKEND</TransitionEquation>
<SourceName>STATE3</SourceName>
<SinkName>STATE4</SinkName>
<SourceConnectorName>Connector</SourceConnectorName>
<SinkConnectorName>Connector</SinkConnectorName>
<SourceArrowSymbol>None</SourceArrowSymbol>
<SinkArrowSymbol>Arrow</SinkArrowSymbol>
<zIndex>0</zIndex>
</CyTransition>
<CyTransition>
<Name>TRANSITION10</Name>
<TransitionEquation>PKEND|SLCS|SLWR</TransitionEquation>
<SourceName>STATE4</SourceName>
<SinkName>STATE1</SinkName>
<SourceConnectorName>Connector</SourceConnectorName>
<SinkConnectorName>Connector</SinkConnectorName>
<SourceArrowSymbol>None</SourceArrowSymbol>
<SinkArrowSymbol>Arrow</SinkArrowSymbol>
<zIndex>0</zIndex>
</CyTransition>
</CyTransitions>
</Root>