This adds support for the OBX daughterboard, a new daughterboard
compatible with the USRP X3x0 series.
- Includes both UHD and CPLD codebases
- Includes CI hooks
Co-authored-by: Javier Valenzuela <javier.valenzuela@emerson.com>
- update job templates with the changes needed to support b206
target (family b2xx)
- add new yaml files
- edit to stages and hw dev tests
- blanked redisHost and devname arg to bypass mutex call for
b2xx devtests
This changes makes the FPGA builds part of the monopipeline. A major
paradigm shift is the notion that the various hardware test pipelines no
longer have a parameter from where to download FPGA artifacts; they now
assume that artifacts are available in the current pipeline. That means
if we want to run a job like job-uhd-rf-tests.yml, we must make sure
that the FPGA artifacts are available, even if that means downloading
the artifacts from a different pipeline and re-uploading them. This has
the additional advantage that failing pipelines now will have all
artifacts directly associated with them.
The way we maintain dependencies correctly in the pipelines, without
having to build all FPGA bitfiles, is that there is a new step for every
bitfile, the "guarantee FPGA artifact step", which has both the
changeset analyzer and the build-fpga steps as a dependency. If the
build-fpga dependency is executed, the guarantee-artifacts step has
to wait until it is complete, but then is a no-op. We use a variable set
by the build-fpga step to identify successful completion of the bitfile
generation.
If the build-fpga dependency is skipped, then we immediately execute the
guarantee-artifacts step, which pulls bitfiles from earlier runs, and
makes them available as artifacts for the rest of the pipeline.
Jobs such as RF tests or streaming tests no longer have the option to
pull bitfiles from wherever. Instead, they assume that the artifacts are
available. An exception is the B200, because we currently don't build
those bitfiles as part of the pipeline.
This adapts the CI scripts such that there is a single pipeline (the
"mono" pipeline) which builds both FPGA bitfiles and all of UHD, and
runs the hardware tests.
Note that this change does not load the FPGA bitfiles built in the same
pipeline, which means this change really enables the same behaviour as
before. Consuming bitfiles created in the same pipeline will be phase
2 of this endeavour.
Previously, the x410 embedded tests and x410 rf tests were part of the
same stage. This commit splits off the x410 RF tests into their own
stage, making it easier to debug RF tests.
This change brings in x410 testing into the uhd
mono pipeline. This also creates a test development
pipeline that executes on uhd mono pipeline as
an upstream artifact source.
Signed-off-by: Steven Koo <steven.koo@ni.com>
