Commit Graph

684 Commits

Author SHA1 Message Date
Wade Fife
0edc35c372 fpga: rfnoc: fft: Support multiple samples per cycle
This adds the NIPC parameter, which configures support for processing
multiple items or samples per clock cycle. With this enabled, the FFT
block can process at rates higher than 250 MSPS, such as 500 MSPS and
beyond.
2025-02-05 17:52:01 -06:00
Wade Fife
3fbddb3872 fpga: rfnoc: fft: Add FFT packetize modules 2025-02-05 16:26:08 -06:00
Wade Fife
d21127c33c fpga: lib: Add AXI-Stream load split and merge modules 2025-02-05 16:26:08 -06:00
Wade Fife
ed9f008b5a fpga: rfnoc: fft: Use DEFAULT on reset in axis_cp_list 2025-02-05 16:26:08 -06:00
Wade Fife
d3ada21915 fpga: sim: Allow DATA_WIDTH that's not a multiple of 8 2025-02-05 16:26:08 -06:00
Wade Fife
a81bf4e9f6 fpga: rfnoc: Add CHDR_HEADER_W constant 2025-02-05 16:26:08 -06:00
Wade Fife
bef123ae1e fpga: lib: Add TO_SIGNED to usrp_utils.svh 2025-02-05 16:26:08 -06:00
Wade Fife
1ad2860413 fpga: tools: Add support for Questa Visualizer 2025-02-05 16:26:08 -06:00
Wade Fife
f1fccacb48 fpga: sim: Add get methods for stall probability 2025-02-05 16:26:08 -06:00
Wade Fife
58cc3f0197 fpga: sim: Remove unused stall arguments
Remove unused stall_probability arguments from
get_master_stall_prob() and get_slave_stall_prob().
2025-02-05 16:26:08 -06:00
Max Köhler
6446c1d351 fpga: lib: add register stage in ipv4 chdr adapter 2025-02-05 16:26:08 -06:00
Max Köhler
0e19a6f356 fpga: x400: refactor 100GEth LBUS to AXI interface 2025-02-05 16:26:08 -06:00
Wade Fife
ce1dfa7940 TEMPORARY: fpga: x400: Add YAML files for X410 FFT builds 2025-02-05 16:16:18 -06:00
Wade Fife
6509d1dc36 fpga: rfnoc: fft: Fix tready on magnitude path
The tready signal that was used when EN_MAGNITUDE equals 0 was not
correct. This commit allows EN_MAGNITUDE to be disabled.
2025-01-21 10:16:14 +01:00
Jörg Hofrichter
d7e91d8d06 ci: enable CI/PR trigger on release branches 2025-01-17 13:28:35 +01:00
Wade Fife
25fffb0067 fpga: rfnoc: Add new FFT block
This replaces the legacy RFNoC FFT block with a new one of the same
name that includes a superset of the original features. New features
include cyclic prefix insertion or removal and FFT sizes up to 64k.
2024-12-17 22:13:42 +01:00
Wade Fife
1549f95dc5 fpga: lib: Add axis_sideband_tuser 2024-12-17 22:13:42 +01:00
Wade Fife
f2a9c389d3 fpga: lib: Add axis_split_bus 2024-12-17 22:13:42 +01:00
Wade Fife
ab19d99cb0 fpga: lib: Add axis_combine 2024-12-17 22:13:42 +01:00
Wade Fife
ec91debff5 fpga: lib: Add axis_data_if_packetize 2024-12-17 22:13:42 +01:00
Wade Fife
d96546d639 fpga: lib: Add Xilinx FFT IP for various configurations 2024-12-17 22:13:42 +01:00
Wade Fife
0d3d69493a fpga: lib: Add complex_to_magphase_int17 IP
The underlying Xilinx CORDIC IP uses 2 bits for the whole part of its
(X,Y) inputs and its magnitude output. So, having 17 bits means we have
enough precision to represent the entire range of an sc16. The 16-bit
CORDIC is insufficient to cover this entire range.
2024-12-17 22:13:42 +01:00
Wade Fife
c2b8eb4a88 fpga: rfnoc: Add SV packages for use with RFNoC 2024-12-17 22:13:42 +01:00
Wade Fife
079fbe5283 fpga: lib: Add usrp_utils.svh with common macros 2024-12-17 22:13:42 +01:00
Wade Fife
76074ecb31 fpga: lib: Cleanup axi_demux module
- Add documentation
- Add generate block labels
- Remove tabs and fix indentation
- Separate the code into three logical sections
2024-12-17 22:13:42 +01:00
Wade Fife
abe1d27c07 fpga: ci: Output JUnit XML for testbench run
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@emerson.com>
2024-12-11 09:08:11 +01:00
Wade Fife
f1ef9ada68 fpga: tools: Add JUnit XML support to run_testbenches
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@emerson.com>
2024-12-11 09:08:11 +01:00
Wade Fife
381ecf8578 fpga: tools: Add --ignore-warnings to repeat_fpga_build 2024-11-27 19:35:33 -06:00
Joerg Hofrichter
0a635d0d11 fpga: x4xx: assemble x410/x440-version-info.dtsi in BUILD_DIR 2024-11-22 08:00:03 +01:00
Max Köhler
a9add0a6a5 fpga: x400: add rf core ctrlport 2024-11-12 15:57:36 -06:00
Joerg Hofrichter
601503e5fa ci: fpga: make changeset analyzer verbose 2024-11-11 08:21:53 +01:00
Joerg Hofrichter
aaa13b81db ci: fpga: Adapted changeset to include RFNoC core BSP files
... which are located at host/include/uhd/rfnoc/core
2024-11-11 08:21:53 +01:00
Martin Braun
53b4d7a210 image builder: Use RADIO_NIPC parameter
This simplifies image core files by generating a RADIO_NIPC parameter
for the X410, X440 and E31x BSP files. The IO port widths for X410 are
now dynamically widened based on the NIPC value, which is a function of
the RF_BW parameter, and cannot be modified.

The radio block can now read the NIPC value from the BSP, and populate
its spc parameter dynamically. This avoids having to know the right spc
value when writing YAML image core files and reduces redundancy.

This also removes the RADIO_NIPC parameter entirely from all the image
core files. This parameter was fine, but it was a bit confusing because
it referenced a Verilog parameter, which you just had to know was there
in the generated Verilog. By referencing the BSP parameter instead, the
YAML files (BSP, radio.yml, and image core file) are now self-contained
regarding the RADIO_NIPC/spc information.

As a minor upside, the input wire widths for X410's and N310's
rfnoc_image_core.sv module are now generated with the correct widths,
and not, as before, with the worst-case width (and then we assume Vivado
will do the right thing).
2024-11-05 15:30:50 +01:00
Max Köhler
77bf8a9d81 fpga: ci: move patches to IT owned share 2024-10-18 10:18:50 +02:00
Martin Braun
eab6e8c7dd ci: fpga: Require requests requisition
The changeset analyzer script requires `requests` to run, so we make
sure it is installed before running the script.
2024-10-17 13:23:53 -05:00
Wade Fife
9998279986 fpga: tools: Add do file for ModelSim 2024-10-08 18:15:52 -05:00
Wade Fife
8ca609f851 fpga: ci: Specify Vivado path for FPGA build 2024-10-07 11:04:13 -05:00
Wade Fife
b6ce5671f8 fpga: tools: Add parallel FPGA build support
Add parallel FPGA build support to repeat_fpga_build.py.
2024-10-07 11:04:13 -05:00
Max Köhler
aa10241c7f fpga: tools: add diamond build sanity checks 2024-09-24 10:24:29 -05:00
Wade Fife
d6ba2dfb5c Fix instances of sim preamble 2024-09-17 08:43:22 -05:00
Joerg Hofrichter
d40db57f2e fpga: e31x/e320/n3xx/x400: Rework device tree file generation
... to support custom image core name, example:

    rfnoc_image_builder -y n310_rfnoc_image_core.yml -n my_custom_name

The device tree source files were renamed to match the target
name used in the Makefile.

    example:
        old: dts/usrp_n310_fpga_hg.dts
        new: dts/N310_HG.dts

The source file is used to compile the final .dts file in the BUILD_DIR.

    example: build-my_custom_name/N310_HG.dts

The final .dts file is copied to the BUILD_OUTPUT_DIR as part of the
post build steps and renamed to the custom image core name.

    example: build/my_custom_name.dts

This completes the change that was introduced with commit 2afc66f132.
2024-09-13 08:44:30 -05:00
mkoop
4c673d8004 ci: fpga: Adapted changeset analyzer rules to folder name change
Adapted changeset analyzer rules change 99865b1, which renamed the
folder host/python/uhd/imgbuilder to host/python/uhd/rfnoc_utils.
This change was made in the "RFNoC OOT overhaul + rfnoc_modtool"
changeset.
2024-09-11 08:54:15 +02:00
Max Köhler
97d108b6f9 fpga: x400: use parameter for RFDC info in RF core full 2024-09-09 10:18:59 -05:00
Wade Fife
00d882455d fpga: ci: Fix target_name for X3xx and X4xx 2024-09-09 10:15:26 -05:00
Wade Fife
26553e3069 fpga: Remove build-usrp dirs when cleaning builds 2024-09-09 10:12:30 -05:00
Wade Fife
2afc66f132 fpga: x400: Make DTS output match bitstream name 2024-09-09 10:12:30 -05:00
Wade Fife
0de3eb63bb fpga: Put dependencies first in Makefile SRCS list 2024-09-06 17:58:33 -05:00
Max Köhler
7e457a190c fpga: x400: add register in 100G Eth TX path for timing 2024-08-30 13:23:29 -05:00
Max Köhler
f407c1cc11 fpga: x440: fix conditional timing constraints 2024-08-27 17:22:35 -05:00
Javier Valenzuela
46216c57d9 fpga: ci: forward intermediate file control 2024-08-27 16:03:12 -05:00