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Merge branch 'fpga_master' into maint

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Josh Blum 2013-04-02 18:49:45 -07:00
commit 36c11bb9f8
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fpga/usrp2/top/E1x0/Makefile.E110
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@ -50,6 +50,7 @@ simulator "ISE Simulator (VHDL/Verilog)" \
TOP_SRCS = \
../B100/u1plus_core.v \
E1x0.v \
E1x0.ucf \
timing.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \