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107 lines
3.0 KiB
Makefile
107 lines
3.0 KiB
Makefile
#
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# Copyright 2008-2012 Ettus Research LLC
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#
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##################################################
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# Project Setup
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##################################################
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TOP_MODULE = E1x0
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BUILD_DIR = $(abspath build$(ISE)-E110)
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# set me in a custom makefile
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CUSTOM_SRCS =
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CUSTOM_DEFS =
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##################################################
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# Include other makefiles
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##################################################
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include ../Makefile.common
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include ../../fifo/Makefile.srcs
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include ../../control_lib/Makefile.srcs
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include ../../sdr_lib/Makefile.srcs
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include ../../serdes/Makefile.srcs
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include ../../simple_gemac/Makefile.srcs
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include ../../timing/Makefile.srcs
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include ../../opencores/Makefile.srcs
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include ../../vrt/Makefile.srcs
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include ../../udp/Makefile.srcs
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include ../../coregen/Makefile.srcs
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include ../../gpmc/Makefile.srcs
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##################################################
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# Project Properties
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##################################################
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export PROJECT_PROPERTIES := \
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family "Spartan-3A DSP" \
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device xc3sd3400a \
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package cs484 \
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speed -4 \
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top_level_module_type "HDL" \
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synthesis_tool "XST (VHDL/Verilog)" \
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simulator "ISE Simulator (VHDL/Verilog)" \
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"Preferred Language" "Verilog" \
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"Enable Message Filtering" FALSE \
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"Display Incremental Messages" FALSE
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##################################################
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# Sources
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##################################################
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TOP_SRCS = \
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../B100/u1plus_core.v \
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E1x0.v \
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E1x0.ucf \
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timing.ucf
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SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
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$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
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$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
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$(GPMC_SRCS)
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##################################################
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# Process Properties
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##################################################
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SYNTHESIZE_PROPERTIES = \
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"Number of Clock Buffers" 8 \
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"Pack I/O Registers into IOBs" Yes \
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"Optimization Effort" High \
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"Optimize Instantiated Primitives" TRUE \
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"Register Balancing" Yes \
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"Use Clock Enable" Auto \
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"Use Synchronous Reset" Auto \
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"Use Synchronous Set" Auto \
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"Verilog Macros" "$(CUSTOM_DEFS)"
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TRANSLATE_PROPERTIES = \
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"Macro Search Path" "$(shell pwd)/../../coregen/"
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MAP_PROPERTIES = \
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"Generate Detailed MAP Report" TRUE \
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"Allow Logic Optimization Across Hierarchy" TRUE \
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"Map to Input Functions" 4 \
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"Optimization Strategy (Cover Mode)" Speed \
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"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
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"Perform Timing-Driven Packing and Placement" TRUE \
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"Map Effort Level" High \
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"Extra Effort" Normal \
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"Combinatorial Logic Optimization" TRUE \
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"Register Duplication" TRUE
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PLACE_ROUTE_PROPERTIES = \
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"Place & Route Effort Level (Overall)" High
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STATIC_TIMING_PROPERTIES = \
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"Number of Paths in Error/Verbose Report" 10 \
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"Report Type" "Error Report"
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GEN_PROG_FILE_PROPERTIES = \
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"Configuration Rate" 6 \
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"Create Binary Configuration File" TRUE \
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"Done (Output Events)" 5 \
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"Enable Bitstream Compression" TRUE \
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"Enable Outputs (Output Events)" 6 \
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"Unused IOB Pins" "Pull Up"
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SIM_MODEL_PROPERTIES = ""
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