uhd/fpga/usrp3
Lars Amsel 29c459f1b3 fpga: enable clock watch circuit on X440 images
Enable clock watch circuit for images with 200 and 400MHz bandwidth
as well. With this we also move from watch the rfdc_clk to watch the
radio_clk. This makes is easier to calculate the max clock rate for
all flavours of images.
2026-08-23 02:17:12 +02:00
..
export/x300/radio fpga: removing deprecated FIFO IP cores 2026-08-20 01:46:19 +02:00
lib doc: fpga: host: Updated Wideband DDC DUC related documentation 2026-08-23 02:03:43 +02:00
sim fpga: dsp: add wideband ddc and duc rfnoc blocks 2026-08-05 08:43:42 +02:00
tools fpga: lib: enable XPM fifo for all Xilinx FPGAs 2026-08-20 01:46:19 +02:00
top fpga: enable clock watch circuit on X440 images 2026-08-23 02:17:12 +02:00
.gitignore Move ignore of build folders into top level 2025-07-18 11:19:52 +02:00
build.py fpga: Replace references to python -> python3 2023-12-05 15:43:08 -06:00
LICENSE.md Merge FPGA repository back into UHD repository 2020-01-28 09:35:36 -08:00