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blocks
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fpga: rfnoc: radio: Add control output FIFO size parameter
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2026-04-30 09:20:13 +02:00 |
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core
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fpga: rfnoc: radio: Add control output FIFO size parameter
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2026-04-30 09:20:13 +02:00 |
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crossbar
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fpga: lib: Add max latency arbitration scheme to axi_mux
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2026-04-29 12:43:04 +02:00 |
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fosphor
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rfnoc: Add RFNoC fosphor block
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2020-04-14 16:37:43 -05:00 |
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sim
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fpga: lib: adjust chdr stream endpoint testbenches due to changed timing
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2026-04-29 12:43:04 +02:00 |
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transport_adapters
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fpga: x4xx: add registers for activity monitoring to ease timing closure
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2025-06-27 17:25:26 -05:00 |
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utils
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fpga: rfnoc: Add CHDR channel demultiplexer module
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2025-07-10 17:09:54 +02:00 |
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xport
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fpga: lib: Add MTU parameter to eth_internal
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2022-09-01 14:41:55 -05:00 |
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xport_sv
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fpga: rfnoc: Move synthesizable code from sim to lib
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2025-03-17 17:47:16 -05:00 |
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.gitignore
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fpga: rfnoc: Remove deprecated files
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2020-08-23 13:52:26 -05:00 |
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addsub.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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addsub.vhd
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_async_stream.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_bit_reduce.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_clip_complex.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_clip_unsigned.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_clip.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_deserializer.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_drop_partial_packet.v
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fpga: rfnoc: fix critical paths in DDC hierarchy
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2025-07-15 10:20:32 +02:00 |
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axi_fir_filter_dec.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_fir_filter.v
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fpga: rfnoc: reverse FIR filter coefficients to get embedded in DSPE48
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2024-04-26 15:19:23 -05:00 |
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axi_join.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_packer.v
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2020-01-28 09:35:36 -08:00 |
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axi_pipe_join.v
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2020-01-28 09:35:36 -08:00 |
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axi_pipe_mac.v
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2020-01-28 09:35:36 -08:00 |
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axi_pipe.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_rate_change.v
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fpga: rfnoc: fix critical paths in DDC hierarchy
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2025-07-15 10:20:32 +02:00 |
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axi_repeat.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_round_and_clip_complex.v
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fpga: lib: fix missing ports in AXI round and clip complex module
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2025-09-29 22:52:22 -05:00 |
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axi_round_and_clip.v
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fpga: lib: refactor round and clip to save resources
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2025-06-27 17:21:36 -05:00 |
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axi_round_complex.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_round.v
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fpga: lib: refactor round and clip to save resources
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2025-06-27 17:21:36 -05:00 |
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axi_serializer.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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axi_sync.v
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fpga: lib: Clean up and document lib files
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2021-08-08 14:59:26 -05:00 |
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axi_tag_time.v
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fpga: rfnoc: fix critical path in DUC hierarchy
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2025-07-15 10:20:32 +02:00 |
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cadd.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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cic_decimate.v
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2020-01-28 09:35:36 -08:00 |
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cic_interpolate.v
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2020-01-28 09:35:36 -08:00 |
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cmul.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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complex_invert.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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complex_to_mag_approx.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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complex_to_magsq.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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conj.v
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2020-01-28 09:35:36 -08:00 |
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const_sreg.v
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2020-01-28 09:35:36 -08:00 |
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const.v
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2020-01-28 09:35:36 -08:00 |
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counter.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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cvita_hdr_decoder.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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cvita_hdr_encoder.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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cvita_hdr_modify.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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cvita_hdr_parser.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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data_types.vh
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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datapath_gatekeeper.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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ddc.v
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fpga: rfnoc: ddc: fix strobe_dds_clip assignment
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2025-08-19 17:55:08 +02:00 |
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dds_freq_tune_duc.v
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fpga: lib: Fix Vivado warnings
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2023-06-09 09:01:04 -05:00 |
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dds_freq_tune.v
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FPGA: Fix warnings in dds_freq_tune module
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2023-01-19 10:05:27 -06:00 |
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dds_timed.v
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fpga: rfnoc: Fix EOB loss in DUC
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2021-08-08 14:59:26 -05:00 |
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dds_wrapper.v
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fpga: rfnoc: Fix EOB loss in DUC
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2021-08-08 14:59:26 -05:00 |
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delay_fifo.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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delay_type2.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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delay_type3.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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delay_type4.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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duc.v
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2020-01-28 09:35:36 -08:00 |
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fft_shift.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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file_sink.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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file_source.v
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fpga: Fix errors found by linting with vsim
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2020-03-23 08:23:51 -05:00 |
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fir_filter_slice.v
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fpga: rfnoc: reverse FIR filter coefficients to get embedded in DSPE48
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2024-04-26 15:19:23 -05:00 |
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join_complex.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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keep_one_in_n.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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Makefile.srcs
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fpga: lib: rfnoc: remove deprecated FIFO modules
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2026-04-27 09:22:10 +02:00 |
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moving_sum.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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mult_add_rc.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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mult_add.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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mult_rc.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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mult.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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multiply.v
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2020-01-28 09:35:36 -08:00 |
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noc_traffic_counter.v
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2020-01-28 09:35:36 -08:00 |
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null_source.v
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2020-01-28 09:35:36 -08:00 |
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periodic_framer.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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phase_accum.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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ram_to_fifo.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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sine_tone.v
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siggen: Fix direction of rotation
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2021-10-27 07:56:09 -07:00 |
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split_complex.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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split_stream_fifo.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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split_stream.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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vector_iir.v
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fpga: rfnoc: Add Vector IIR RFNoC block
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2020-05-19 14:22:55 -05:00 |
