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uhd/fpga/usrp3/lib/packet_proc
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Andrew Moch dd9847c5c3 fpga: lib: Pipeline and add clken to ip_hdr_checksum 
Adds LATENCY parameter to control the ammount of pieplineing. Adds a
clock enable to control the advance of the pipeline.

Used in xport when calculating new UDP headers for CHDR traffic.
2020-06-24 09:55:14 -05:00
..
arp_responder Merge FPGA repository back into UHD repository 2020-01-28 09:35:36 -08:00
.gitignore Merge FPGA repository back into UHD repository 2020-01-28 09:35:36 -08:00
arm_deframer.v Merge FPGA repository back into UHD repository 2020-01-28 09:35:36 -08:00
axis_to_cvita.v Merge FPGA repository back into UHD repository 2020-01-28 09:35:36 -08:00
chdr_chunker.v Merge FPGA repository back into UHD repository 2020-01-28 09:35:36 -08:00
chdr_dechunker.v Merge FPGA repository back into UHD repository 2020-01-28 09:35:36 -08:00
cvita_dest_lookup.v Merge FPGA repository back into UHD repository 2020-01-28 09:35:36 -08:00
cvita_to_axis.v Merge FPGA repository back into UHD repository 2020-01-28 09:35:36 -08:00
ip_hdr_checksum.v fpga: lib: Pipeline and add clken to ip_hdr_checksum 2020-06-24 09:55:14 -05:00
Makefile.srcs Merge FPGA repository back into UHD repository 2020-01-28 09:35:36 -08:00