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dts
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fpga: e31x/e320/n3xx/x400: Rework device tree file generation
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2024-09-13 08:44:30 -05:00 |
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ip
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fpga: e31x: Upgrade to Vivado 2025.2
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2026-09-29 09:09:08 +02:00 |
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sim
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fpga: sim: Add to DESIGN_SRCS rather than replace
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2026-06-29 08:08:59 +02:00 |
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.gitignore
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Move ignore of build folders into top level
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2025-07-18 11:19:52 +02:00 |
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axi_pmu.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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build_e31x.tcl
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fpga: remove synth target
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2026-06-30 10:33:29 +02:00 |
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e31x_core.v
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rfnoc: add pps IO signature for all targets
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2026-01-13 12:38:50 +01:00 |
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e31x_dram.v
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fpga: e31x: Add DRAM support
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2022-02-10 18:13:44 -07:00 |
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e31x_idle_pins.xdc
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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e31x_idle.v
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e31x: Swap out liberio for internal ethernet in the idle image
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2020-07-18 11:52:58 -05:00 |
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e31x_pins.xdc
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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e31x_timing.xdc
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fpga: e31x: Update constraints to avoid timing issues
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2020-04-08 17:24:15 -05:00 |
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e31x.v
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fpga: e31x: fix GPIO direction signal
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2025-09-16 08:21:19 +02:00 |
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e310_io.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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e310_rfnoc_image_core.yml
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fpga: fix typo in yml files
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2026-08-28 16:09:35 +01:00 |
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Makefile
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fpga: remove synth target
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2026-06-30 10:33:29 +02:00 |
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Makefile.e31x.inc
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fpga: remove synth target
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2026-06-30 10:33:29 +02:00 |
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ppsloop.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
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setupenv.sh
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fpga: e31x: Upgrade to Vivado 2025.2
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2026-09-29 09:09:08 +02:00 |
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spi_slave.v
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Merge FPGA repository back into UHD repository
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2020-01-28 09:35:36 -08:00 |
