Added 'module_serial' field to retured value of
multi_usrp::get_usrp_rx_info() and multi_usrp::get_usrp_tx_info() API
calls that provides the module serial number.
Signed-off-by: michael-west <michael.west@ettus.com>
Only the make_x4xx target existed and did not actually run any tests.
Added correct mapping for make_x410 and make_x440 devtest targets.
Removed make_x4xx target.
Signed-off-by: michael-west <michael.west@ettus.com>
This example demonstrates the simultaneous capture of the entire L-band
which extends from 1 GHz to 2.4 GHz using one channel on each of the two
radios using the dual rate feature. This is supported ionly on the X440 device.
Read the comments in the example for details.
Does the following:
- Sets up connections in rfnoc graph
- Configures radios and dual replay blocks
- Synchronously captures data and streams to replay block
- Fetches data to host and plots a windowed FFT.
- Repeat.
Signed-off-by: Virendra Kakade <virendra.kakade@ni.com>
Co-authored-by: Martin Anderseck <martin.anderseck@ni.com>
This updates the block registry for x400_radio_control to query the
clock information from the FPGA/MPM. This will require an up-to-date
bitfile and MPM.
If the bitfile is not up-to-date, there will be an error message asking
the user to update the bitfile. If MPM is not up to date, it will fail
to detect clock indices '4' and '5'.
This updates the RFNoC image cores to separate the two DRAM banks on
X4xx by splitting them into "dram0" and "dram1". Previously, both DRAM
banks shared the same DRAM port, named "dram", which created some
confusion.
The Replay block has also been duplicated in the bitstreams that use
both banks, so we now have one Replay block per bank.
- Update X410 and X440 BSP YAML files to properly index clocks
- Update image core files to declare clock indices
- Update get_clocks() in MPM to return the correct values
This does not include changes to the x400_radio_control block registry.
This change by itself will thus not change behaviour.
During creation of the RFNoC graph, the block registry is queried to
identify the clocks used for timebase and control. This adds the option
to ask the FPGA instead (via backend interface).
Adds a 266.667 MHz compute engine clock and uses it instead of the
radio clock for the DDC and DUC. Using a faster clock than the radio
allows the DDC and DUC to drain after a stall in the data flow.
Adds a 266.667 MHz compute engine clock and uses it instead of the
radio clock for the DDC and DUC. Using a faster clock than the radio
allows the DDC and DUC to drain after a stall in the data flow.
- Image core files can now provide timebase_clock and ctrl_clock fields
to blocks, which will populate the backend interface accordingly.
- Clocks ports now have a direction associated (in, out).
When query_gpsdo_sensors creates a multi_usrp object with no additional device args,
it initializes the device using clock_source and time_source values of 'internal'.
Later, it sets them to 'gpsdo'. Since the x4xx devices put the GPSDO module in
reset when not being used, it takes several minutes to re-establish a GPS lock
after selecting the 'gpsdo' clock/time sources. By creating the multi_usrp object
using clock/time source values of 'gpsdo', the GPSDO isn't disabled and re-enabled
each run and the GPSDO is able to get a lock after enough time passes.
Change the syrnchronization order to be following:
- Run the MTS (multi-tile sync) procedure
- Run the timekeeper alignment to next_pps edge
- Run the post timekeeper alignment steps (none for now)
This ensures that any effects caused due to delay adjustments which are
part of the MTS procedure do not affect timekeeper alignment.
Without this change timekeepers on two X4xx devices would be mis-aligned
slightly in a multi-device scenario.
Note that setting all timekeepers to a common time_spec on the next_pps
as a part of post-initialization application code will still align them perfectly.
Signed-off-by: Virendra Kakade <virendra.kakade@ni.com>
Initially the threshold was suitable for the cal tone at the original
frequency of 100 MHz. Since this was changed and because it can be
configured via the cal_freq parameter anyway we need to take care to
allow lower input levels that we might have at different frequencies.
In addition we know that for the background calibration of the chip a
signal of >=-46 dBm is required, so by using -20 dBm (which corresponds
to the 14-bit dbFS value of 1465) we still have some margin to recognize
any broken components.
Modify the cal_freq used in the calibration procedure by X440 devices
which use the FBX daughterboard. The new value obeys the rules that are
specified mainly in the PG269 to help the background calibration (BG)
run under better conditions and hence improve our input spur performance.
Signed-off-by: Virendra Kakade <virendra.kakade@ni.com>
Co-authored-by: Volkan Öz <volkan.oez@ni.com>
Replaced newly added paragraph with subsubsection elements that resulted into
an as warning declared build error when buildin on readthedocs.
The build service still uses doxygen 1.8.13, which failed to include content
into the generated html after the warning was reported. Newer version of
doxygen also report the warning/s but continue including content.
- Extended FPGA Image Flavors sections
- Extended MCR and Converter Rates section
- Added Page for FBX daughterboard
- Added FBX_simplified_blockdiagram.png that is referenced by
FBX daughterboard page and represents one transceiver chain.
- Added known issue regarding need for restarting MPM when mcr is
changed and potential of dynamic QSFP28 configurations may getting
lost.
Change all references to "gps_lock" to "gps_locked" for consistency
across the code base. Fixes incorrect use of "gps_lock" for the sensor
name on X4xx.
Signed-off-by: michael-west <michael.west@ettus.com>
- Add section on X4x0 devices, explaining that X440 has 2 timekeepers
- Expand docs on mb_controller::timekeeper
- Provide more context on multi_usrp time-related calls
Some files in the source tree need some treatment before clang-format
can automatically be applied to all files.
This commit adds some 'clang-format off' statements and some manual
pre-formatting in order to not cause havoc when clang-format is applied
to the entire source tree.
