10 Commits

Author	SHA1	Message	Date
Martin Braun	31b8d05c3d	Updated compat numbers for B2x0 and X3x0 ... - B2x0: FW compat number (goes with previous firmware update) - X3x0: Max HW rev number	2015-07-14 15:34:32 -07:00
Balint Seeber	6d0f1ee6f6	fx3: New firmware features: Logging, more configuration ... - Logging in conjunction with B200 side-channel utility (using UART or directly over USB) - More and better configurability, e.g. Tx voltage swing and DMA configuration	2015-07-14 11:52:21 -07:00
Ben Hilburn	90cc498983	FX3: Updating FW to support NI-USRP VID and PIDs ... Conflicts: firmware/fx3/b200/b200_usb_descriptors.c	2015-04-15 17:05:24 -07:00
Ben Hilburn	069cd969ef	FX3: Updating FX3 FW build docs ... Conflicts: firmware/fx3/README.md	2015-04-15 17:03:51 -07:00
Ashish Chaudhari	9da89f46f0	b200: Bumped FX3 firmware compat number to 7.	2014-10-01 16:06:35 -07:00
Martin Braun	0ca4b4f854	docs: Added a note on FX3 SDK version	2014-10-01 12:56:33 -07:00
Ashish Chaudhari	145f1d7cf7	b200: Removed all AD9361 related firmware ... - FX3 does not respond to AD9361 firmware transaction VREQs - FX3 does not respond to AD9361 SPI transaction VREQs - Deleted all AD9361 firmware files - Bumped FW compat to 6	2014-08-12 11:19:22 -07:00
Ashish Chaudhari	ef5abde4f0	b200: AD9361 firmware bugfixes ... - Fix for BUG #485: B200: Channels Swap Between Runs # Added code to transition state machine out of FDD while reconfiguring active chains. # bb:0b9929 Mon Jun 16 14:56:26 2014 -0700 - Fix for BUG #500: B210: RX channels are not phase aligned # Set bit to invert RX if internal LNA is bypassed # bb:0a4565 Thu Jun 5 17:10:37 2014 -0700	2014-08-01 13:19:41 -07:00
Ashish Chaudhari	c7274790a0	b200: Moved AD9361 driver to host ... - Switched to FPGA SPI engine - Moved firmware AD9361 driver to UHD - Bumped FW compat to 5, FPGA compat to 4 - Known Issue: AD9361 SPI rate is too slow	2014-08-01 13:14:56 -07:00
Ben Hilburn	642f3fb582	b2xx: Pulling FX3 and AD9361 source code into master.	2014-04-07 14:58:25 -07:00