mirror of
https://github.com/EttusResearch/uhd.git
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fpga: b300: Upgrade to Vivado 2025.2
This commit is contained in:
Max Köhler
Max Köhler
parent
4e8fa298dd
commit
f3d6cd6c01
@ -238,12 +238,19 @@ module b310
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.clk_in1 (bus_clk_in) //input wire
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);
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logic dev_clk;
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logic radio_clk;
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logic radio_clk_2x;
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logic radio_clk_gen_locked;
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logic radio_clk_shifted;
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logic radio_clk_gen_rst;
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IBUFDS IBUFDS_ref_clk (
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.O(dev_clk),
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.I(DEVCLK_P),
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.IB(DEVCLK_N)
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);
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radio_clk_gen radio_clk_gen_i (
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.clk_out1 (radio_clk), //output wire
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.clk_out2 (radio_clk_2x), //output wire
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@ -251,8 +258,7 @@ module b310
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.clk_out4 (radio_clk_shifted), //output wire
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.reset (radio_clk_gen_rst), //input wire
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.locked (radio_clk_gen_locked), //output wire
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.clk_in1_p(DEVCLK_P), //input wire
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.clk_in1_n(DEVCLK_N) //input wire
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.clk_in1 (dev_clk) //input wire
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);
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@ -20,13 +20,19 @@ set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2021.1
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set scripts_vivado_version 2025.2
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."}
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} else {
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catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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}
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return 1
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}
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@ -284,35 +290,38 @@ proc create_root_design { parentCell } {
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# Create instance: m00_rs, and set properties
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set m00_rs [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 m00_rs ]
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set_property -dict [ list \
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CONFIG.REG_AR {1} \
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CONFIG.REG_AW {1} \
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CONFIG.REG_B {1} \
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set_property -dict [list \
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CONFIG.REG_AR {7} \
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CONFIG.REG_AW {7} \
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CONFIG.REG_B {7} \
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] $m00_rs
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# Create instance: s00_rs_0, and set properties
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set s00_rs_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s00_rs_0 ]
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set_property -dict [ list \
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CONFIG.REG_AR {1} \
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CONFIG.REG_AW {1} \
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CONFIG.REG_B {1} \
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set_property -dict [list \
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CONFIG.REG_AR {7} \
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CONFIG.REG_AW {7} \
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CONFIG.REG_B {7} \
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CONFIG.REG_R {1} \
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CONFIG.REG_W {1} \
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] $s00_rs_0
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# Create instance: s00_rs_1, and set properties
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set s00_rs_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s00_rs_1 ]
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set_property -dict [ list \
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CONFIG.REG_AR {1} \
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CONFIG.REG_AW {1} \
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CONFIG.REG_B {1} \
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set_property -dict [list \
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CONFIG.REG_AR {7} \
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CONFIG.REG_AW {7} \
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CONFIG.REG_B {7} \
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CONFIG.REG_R {1} \
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CONFIG.REG_W {1} \
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] $s00_rs_1
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# Create instance: s00_width_conv, and set properties
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set s00_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s00_width_conv ]
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set_property -dict [ list \
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set_property -dict [list \
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CONFIG.ACLK_ASYNC {1} \
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CONFIG.FIFO_MODE {2} \
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CONFIG.MI_DATA_WIDTH {256} \
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@ -320,29 +329,32 @@ proc create_root_design { parentCell } {
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CONFIG.SYNCHRONIZATION_STAGES {2} \
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] $s00_width_conv
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# Create instance: s01_rs_0, and set properties
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set s01_rs_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s01_rs_0 ]
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set_property -dict [ list \
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CONFIG.REG_AR {1} \
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CONFIG.REG_AW {1} \
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CONFIG.REG_B {1} \
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set_property -dict [list \
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CONFIG.REG_AR {7} \
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CONFIG.REG_AW {7} \
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CONFIG.REG_B {7} \
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CONFIG.REG_R {1} \
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CONFIG.REG_W {1} \
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] $s01_rs_0
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# Create instance: s01_rs_1, and set properties
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set s01_rs_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s01_rs_1 ]
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set_property -dict [ list \
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CONFIG.REG_AR {1} \
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CONFIG.REG_AW {1} \
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CONFIG.REG_B {1} \
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set_property -dict [list \
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CONFIG.REG_AR {7} \
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CONFIG.REG_AW {7} \
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CONFIG.REG_B {7} \
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CONFIG.REG_R {1} \
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CONFIG.REG_W {1} \
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] $s01_rs_1
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# Create instance: s01_width_conv, and set properties
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set s01_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s01_width_conv ]
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set_property -dict [ list \
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set_property -dict [list \
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CONFIG.ACLK_ASYNC {1} \
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CONFIG.FIFO_MODE {2} \
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CONFIG.MI_DATA_WIDTH {256} \
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@ -350,31 +362,367 @@ proc create_root_design { parentCell } {
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CONFIG.SYNCHRONIZATION_STAGES {2} \
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] $s01_width_conv
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# Create instance: xbar, and set properties
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set xbar [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 xbar ]
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set_property -dict [ list \
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set_property -dict [list \
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CONFIG.DATA_WIDTH {256} \
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CONFIG.ID_WIDTH {1} \
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CONFIG.M00_A01_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A02_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A03_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A04_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A05_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A06_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A07_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A08_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A09_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A10_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A11_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A12_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A13_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A14_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_A15_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M00_READ_ISSUING {8} \
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CONFIG.M00_WRITE_ISSUING {8} \
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CONFIG.M01_A00_ADDR_WIDTH {0} \
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CONFIG.M01_A00_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A01_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A02_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A03_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A04_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A05_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A06_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A07_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A08_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A09_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A10_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A11_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A12_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A13_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A14_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_A15_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M01_READ_ISSUING {8} \
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CONFIG.M01_WRITE_ISSUING {8} \
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CONFIG.M02_A00_ADDR_WIDTH {0} \
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CONFIG.M02_A00_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A01_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A02_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A03_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A04_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A05_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A06_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A07_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A08_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A09_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A10_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A11_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A12_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A13_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A14_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_A15_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M02_READ_ISSUING {8} \
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CONFIG.M02_WRITE_ISSUING {8} \
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CONFIG.M03_A00_ADDR_WIDTH {0} \
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CONFIG.M03_A00_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A01_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A02_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A03_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A04_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A05_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A06_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A07_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A08_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A09_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A10_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A11_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A12_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A13_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A14_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_A15_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M03_READ_ISSUING {8} \
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CONFIG.M03_WRITE_ISSUING {8} \
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CONFIG.M04_A00_ADDR_WIDTH {0} \
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CONFIG.M04_A00_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M04_A01_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M04_A02_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M04_A03_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M04_A04_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M04_A05_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M04_A06_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M04_A07_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M04_A08_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M04_A09_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M04_A10_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M04_A11_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M04_A12_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M04_A13_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M04_A14_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M04_A15_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M04_READ_ISSUING {8} \
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CONFIG.M04_WRITE_ISSUING {8} \
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CONFIG.M05_A00_ADDR_WIDTH {0} \
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CONFIG.M05_A00_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M05_A01_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M05_A02_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M05_A03_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M05_A04_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M05_A05_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M05_A06_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M05_A07_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M05_A08_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M05_A09_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M05_A10_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M05_A11_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M05_A12_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M05_A13_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M05_A14_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M05_A15_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M05_READ_ISSUING {8} \
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CONFIG.M05_WRITE_ISSUING {8} \
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CONFIG.M06_A00_ADDR_WIDTH {0} \
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CONFIG.M06_A00_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M06_A01_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M06_A02_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M06_A03_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M06_A04_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M06_A05_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M06_A06_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M06_A07_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M06_A08_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M06_A09_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M06_A10_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M06_A11_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M06_A12_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M06_A13_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M06_A14_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M06_A15_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M06_READ_ISSUING {8} \
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CONFIG.M06_WRITE_ISSUING {8} \
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CONFIG.M07_A00_ADDR_WIDTH {0} \
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CONFIG.M07_A00_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M07_A01_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M07_A02_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M07_A03_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M07_A04_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M07_A05_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M07_A06_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M07_A07_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M07_A08_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M07_A09_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M07_A10_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M07_A11_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M07_A12_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M07_A13_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M07_A14_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M07_A15_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M07_READ_ISSUING {8} \
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CONFIG.M07_WRITE_ISSUING {8} \
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CONFIG.M08_A00_ADDR_WIDTH {0} \
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CONFIG.M08_A00_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M08_A01_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M08_A02_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M08_A03_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M08_A04_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M08_A05_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M08_A06_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M08_A07_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M08_A08_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M08_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A10_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M08_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A12_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M08_A13_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M08_A14_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M08_A15_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M08_READ_ISSUING {8} \
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CONFIG.M08_WRITE_ISSUING {8} \
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CONFIG.M09_A00_ADDR_WIDTH {0} \
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CONFIG.M09_A00_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M09_A01_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M09_A02_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M09_A03_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M09_A04_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M09_A05_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M09_A06_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M09_A07_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M09_A08_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M09_A09_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M09_A10_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M09_A11_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M09_A12_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M09_A13_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M09_A14_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M09_A15_BASE_ADDR {0xffffffffffffffff} \
|
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CONFIG.M09_READ_ISSUING {8} \
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CONFIG.M09_WRITE_ISSUING {8} \
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CONFIG.M10_A00_ADDR_WIDTH {0} \
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CONFIG.M10_A00_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M10_A01_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M10_A02_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M10_A03_BASE_ADDR {0xffffffffffffffff} \
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CONFIG.M10_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_READ_ISSUING {8} \
|
||||
CONFIG.M10_WRITE_ISSUING {8} \
|
||||
CONFIG.M11_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M11_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_READ_ISSUING {8} \
|
||||
CONFIG.M11_WRITE_ISSUING {8} \
|
||||
CONFIG.M12_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M12_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_READ_ISSUING {8} \
|
||||
CONFIG.M12_WRITE_ISSUING {8} \
|
||||
CONFIG.M13_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M13_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_READ_ISSUING {8} \
|
||||
CONFIG.M13_WRITE_ISSUING {8} \
|
||||
CONFIG.M14_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M14_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_READ_ISSUING {8} \
|
||||
CONFIG.M14_WRITE_ISSUING {8} \
|
||||
CONFIG.M15_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M15_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_READ_ISSUING {8} \
|
||||
CONFIG.M15_WRITE_ISSUING {8} \
|
||||
CONFIG.NUM_MI {1} \
|
||||
CONFIG.NUM_SI {2} \
|
||||
CONFIG.S00_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S00_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S01_BASE_ID {0x00000001} \
|
||||
CONFIG.S01_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S01_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S02_BASE_ID {0x00000002} \
|
||||
CONFIG.S02_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S02_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S03_BASE_ID {0x00000003} \
|
||||
CONFIG.S03_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S03_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S04_BASE_ID {0x00000004} \
|
||||
CONFIG.S04_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S04_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S05_BASE_ID {0x00000005} \
|
||||
CONFIG.S05_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S05_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S06_BASE_ID {0x00000006} \
|
||||
CONFIG.S06_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S06_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S07_BASE_ID {0x00000007} \
|
||||
CONFIG.S07_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S07_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S08_BASE_ID {0x00000008} \
|
||||
CONFIG.S08_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S08_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S09_BASE_ID {0x00000009} \
|
||||
CONFIG.S09_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S09_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S10_BASE_ID {0x0000000a} \
|
||||
CONFIG.S10_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S10_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S11_BASE_ID {0x0000000b} \
|
||||
CONFIG.S11_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S11_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S12_BASE_ID {0x0000000c} \
|
||||
CONFIG.S12_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S12_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S13_BASE_ID {0x0000000d} \
|
||||
CONFIG.S13_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S13_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S14_BASE_ID {0x0000000e} \
|
||||
CONFIG.S14_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S14_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S15_BASE_ID {0x0000000f} \
|
||||
CONFIG.S15_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S15_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.STRATEGY {2} \
|
||||
] $xbar
|
||||
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports S00_AXI] [get_bd_intf_pins s00_rs_0/S_AXI]
|
||||
connect_bd_intf_net -intf_net S01_AXI_1 [get_bd_intf_ports S01_AXI] [get_bd_intf_pins s01_rs_0/S_AXI]
|
||||
@ -388,12 +736,32 @@ proc create_root_design { parentCell } {
|
||||
connect_bd_intf_net -intf_net xbar_M00_AXI [get_bd_intf_pins m00_rs/S_AXI] [get_bd_intf_pins xbar/M00_AXI]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net M00_AXI_ACLK_1 [get_bd_ports M00_AXI_ACLK] [get_bd_pins m00_rs/aclk] [get_bd_pins s00_rs_1/aclk] [get_bd_pins s00_width_conv/m_axi_aclk] [get_bd_pins s01_rs_1/aclk] [get_bd_pins s01_width_conv/m_axi_aclk] [get_bd_pins xbar/aclk]
|
||||
connect_bd_net -net M00_AXI_ARESETN_1 [get_bd_ports M00_AXI_ARESETN] [get_bd_pins m00_rs/aresetn] [get_bd_pins s00_rs_1/aresetn] [get_bd_pins s00_width_conv/m_axi_aresetn] [get_bd_pins s01_rs_1/aresetn] [get_bd_pins s01_width_conv/m_axi_aresetn] [get_bd_pins xbar/aresetn]
|
||||
connect_bd_net -net S00_AXI_ACLK_1 [get_bd_ports S00_AXI_ACLK] [get_bd_pins s00_rs_0/aclk] [get_bd_pins s00_width_conv/s_axi_aclk]
|
||||
connect_bd_net -net S00_AXI_ARESETN_1 [get_bd_ports S00_AXI_ARESETN] [get_bd_pins s00_rs_0/aresetn] [get_bd_pins s00_width_conv/s_axi_aresetn]
|
||||
connect_bd_net -net S01_AXI_ACLK_1 [get_bd_ports S01_AXI_ACLK] [get_bd_pins s01_rs_0/aclk] [get_bd_pins s01_width_conv/s_axi_aclk]
|
||||
connect_bd_net -net S01_AXI_ARESETN_1 [get_bd_ports S01_AXI_ARESETN] [get_bd_pins s01_rs_0/aresetn] [get_bd_pins s01_width_conv/s_axi_aresetn]
|
||||
connect_bd_net -net M00_AXI_ACLK_1 [get_bd_ports M00_AXI_ACLK] \
|
||||
[get_bd_pins m00_rs/aclk] \
|
||||
[get_bd_pins s00_rs_1/aclk] \
|
||||
[get_bd_pins s00_width_conv/m_axi_aclk] \
|
||||
[get_bd_pins s01_rs_1/aclk] \
|
||||
[get_bd_pins s01_width_conv/m_axi_aclk] \
|
||||
[get_bd_pins xbar/aclk]
|
||||
connect_bd_net -net M00_AXI_ARESETN_1 [get_bd_ports M00_AXI_ARESETN] \
|
||||
[get_bd_pins m00_rs/aresetn] \
|
||||
[get_bd_pins s00_rs_1/aresetn] \
|
||||
[get_bd_pins s00_width_conv/m_axi_aresetn] \
|
||||
[get_bd_pins s01_rs_1/aresetn] \
|
||||
[get_bd_pins s01_width_conv/m_axi_aresetn] \
|
||||
[get_bd_pins xbar/aresetn]
|
||||
connect_bd_net -net S00_AXI_ACLK_1 [get_bd_ports S00_AXI_ACLK] \
|
||||
[get_bd_pins s00_rs_0/aclk] \
|
||||
[get_bd_pins s00_width_conv/s_axi_aclk]
|
||||
connect_bd_net -net S00_AXI_ARESETN_1 [get_bd_ports S00_AXI_ARESETN] \
|
||||
[get_bd_pins s00_rs_0/aresetn] \
|
||||
[get_bd_pins s00_width_conv/s_axi_aresetn]
|
||||
connect_bd_net -net S01_AXI_ACLK_1 [get_bd_ports S01_AXI_ACLK] \
|
||||
[get_bd_pins s01_rs_0/aclk] \
|
||||
[get_bd_pins s01_width_conv/s_axi_aclk]
|
||||
connect_bd_net -net S01_AXI_ARESETN_1 [get_bd_ports S01_AXI_ARESETN] \
|
||||
[get_bd_pins s01_rs_0/aresetn] \
|
||||
[get_bd_pins s01_width_conv/s_axi_aresetn]
|
||||
|
||||
# Create address segments
|
||||
assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces S00_AXI] [get_bd_addr_segs M00_AXI/Reg] -force
|
||||
|
||||
@ -20,13 +20,19 @@ set script_folder [_tcl::get_script_folder]
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2021.1
|
||||
set scripts_vivado_version 2025.2
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."}
|
||||
|
||||
} else {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
}
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
@ -193,6 +199,7 @@ proc create_root_design { parentCell } {
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {32} \
|
||||
CONFIG.DATA_WIDTH {256} \
|
||||
CONFIG.FREQ_HZ {1000000000} \
|
||||
CONFIG.NUM_READ_OUTSTANDING {2} \
|
||||
CONFIG.NUM_WRITE_OUTSTANDING {2} \
|
||||
CONFIG.PROTOCOL {AXI4} \
|
||||
@ -205,7 +212,7 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.AWUSER_WIDTH {0} \
|
||||
CONFIG.BUSER_WIDTH {0} \
|
||||
CONFIG.DATA_WIDTH {64} \
|
||||
CONFIG.FREQ_HZ {1000000000} \
|
||||
CONFIG.FREQ_HZ {2000000000} \
|
||||
CONFIG.HAS_BRESP {1} \
|
||||
CONFIG.HAS_BURST {1} \
|
||||
CONFIG.HAS_CACHE {1} \
|
||||
@ -237,7 +244,7 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.AWUSER_WIDTH {0} \
|
||||
CONFIG.BUSER_WIDTH {0} \
|
||||
CONFIG.DATA_WIDTH {64} \
|
||||
CONFIG.FREQ_HZ {1000000000} \
|
||||
CONFIG.FREQ_HZ {2000000000} \
|
||||
CONFIG.HAS_BRESP {1} \
|
||||
CONFIG.HAS_BURST {1} \
|
||||
CONFIG.HAS_CACHE {1} \
|
||||
@ -269,7 +276,7 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.AWUSER_WIDTH {0} \
|
||||
CONFIG.BUSER_WIDTH {0} \
|
||||
CONFIG.DATA_WIDTH {64} \
|
||||
CONFIG.FREQ_HZ {1000000000} \
|
||||
CONFIG.FREQ_HZ {2000000000} \
|
||||
CONFIG.HAS_BRESP {1} \
|
||||
CONFIG.HAS_BURST {1} \
|
||||
CONFIG.HAS_CACHE {1} \
|
||||
@ -301,7 +308,7 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.AWUSER_WIDTH {0} \
|
||||
CONFIG.BUSER_WIDTH {0} \
|
||||
CONFIG.DATA_WIDTH {64} \
|
||||
CONFIG.FREQ_HZ {1000000000} \
|
||||
CONFIG.FREQ_HZ {2000000000} \
|
||||
CONFIG.HAS_BRESP {1} \
|
||||
CONFIG.HAS_BURST {1} \
|
||||
CONFIG.HAS_CACHE {1} \
|
||||
@ -361,35 +368,38 @@ proc create_root_design { parentCell } {
|
||||
|
||||
# Create instance: m00_rs, and set properties
|
||||
set m00_rs [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 m00_rs ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
set_property -dict [list \
|
||||
CONFIG.REG_AR {7} \
|
||||
CONFIG.REG_AW {7} \
|
||||
CONFIG.REG_B {7} \
|
||||
] $m00_rs
|
||||
|
||||
|
||||
# Create instance: s00_rs_0, and set properties
|
||||
set s00_rs_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s00_rs_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
set_property -dict [list \
|
||||
CONFIG.REG_AR {7} \
|
||||
CONFIG.REG_AW {7} \
|
||||
CONFIG.REG_B {7} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s00_rs_0
|
||||
|
||||
|
||||
# Create instance: s00_rs_1, and set properties
|
||||
set s00_rs_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s00_rs_1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
set_property -dict [list \
|
||||
CONFIG.REG_AR {7} \
|
||||
CONFIG.REG_AW {7} \
|
||||
CONFIG.REG_B {7} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s00_rs_1
|
||||
|
||||
|
||||
# Create instance: s00_width_conv, and set properties
|
||||
set s00_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s00_width_conv ]
|
||||
set_property -dict [ list \
|
||||
set_property -dict [list \
|
||||
CONFIG.ACLK_ASYNC {1} \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.MI_DATA_WIDTH {256} \
|
||||
@ -397,29 +407,32 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.SYNCHRONIZATION_STAGES {2} \
|
||||
] $s00_width_conv
|
||||
|
||||
|
||||
# Create instance: s01_rs_0, and set properties
|
||||
set s01_rs_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s01_rs_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
set_property -dict [list \
|
||||
CONFIG.REG_AR {7} \
|
||||
CONFIG.REG_AW {7} \
|
||||
CONFIG.REG_B {7} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s01_rs_0
|
||||
|
||||
|
||||
# Create instance: s01_rs_1, and set properties
|
||||
set s01_rs_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s01_rs_1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
set_property -dict [list \
|
||||
CONFIG.REG_AR {7} \
|
||||
CONFIG.REG_AW {7} \
|
||||
CONFIG.REG_B {7} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s01_rs_1
|
||||
|
||||
|
||||
# Create instance: s01_width_conv, and set properties
|
||||
set s01_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s01_width_conv ]
|
||||
set_property -dict [ list \
|
||||
set_property -dict [list \
|
||||
CONFIG.ACLK_ASYNC {1} \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.MI_DATA_WIDTH {256} \
|
||||
@ -427,29 +440,32 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.SYNCHRONIZATION_STAGES {2} \
|
||||
] $s01_width_conv
|
||||
|
||||
|
||||
# Create instance: s02_rs_0, and set properties
|
||||
set s02_rs_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s02_rs_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
set_property -dict [list \
|
||||
CONFIG.REG_AR {7} \
|
||||
CONFIG.REG_AW {7} \
|
||||
CONFIG.REG_B {7} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s02_rs_0
|
||||
|
||||
|
||||
# Create instance: s02_rs_1, and set properties
|
||||
set s02_rs_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s02_rs_1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
set_property -dict [list \
|
||||
CONFIG.REG_AR {7} \
|
||||
CONFIG.REG_AW {7} \
|
||||
CONFIG.REG_B {7} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s02_rs_1
|
||||
|
||||
|
||||
# Create instance: s02_width_conv, and set properties
|
||||
set s02_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s02_width_conv ]
|
||||
set_property -dict [ list \
|
||||
set_property -dict [list \
|
||||
CONFIG.ACLK_ASYNC {1} \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.MI_DATA_WIDTH {256} \
|
||||
@ -457,29 +473,32 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.SYNCHRONIZATION_STAGES {2} \
|
||||
] $s02_width_conv
|
||||
|
||||
|
||||
# Create instance: s03_rs_0, and set properties
|
||||
set s03_rs_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s03_rs_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
set_property -dict [list \
|
||||
CONFIG.REG_AR {7} \
|
||||
CONFIG.REG_AW {7} \
|
||||
CONFIG.REG_B {7} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s03_rs_0
|
||||
|
||||
|
||||
# Create instance: s03_rs_1, and set properties
|
||||
set s03_rs_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s03_rs_1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.REG_AR {1} \
|
||||
CONFIG.REG_AW {1} \
|
||||
CONFIG.REG_B {1} \
|
||||
set_property -dict [list \
|
||||
CONFIG.REG_AR {7} \
|
||||
CONFIG.REG_AW {7} \
|
||||
CONFIG.REG_B {7} \
|
||||
CONFIG.REG_R {1} \
|
||||
CONFIG.REG_W {1} \
|
||||
] $s03_rs_1
|
||||
|
||||
|
||||
# Create instance: s03_width_conv, and set properties
|
||||
set s03_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s03_width_conv ]
|
||||
set_property -dict [ list \
|
||||
set_property -dict [list \
|
||||
CONFIG.ACLK_ASYNC {1} \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.MI_DATA_WIDTH {256} \
|
||||
@ -487,31 +506,367 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.SYNCHRONIZATION_STAGES {2} \
|
||||
] $s03_width_conv
|
||||
|
||||
|
||||
# Create instance: xbar, and set properties
|
||||
set xbar [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 xbar ]
|
||||
set_property -dict [ list \
|
||||
set_property -dict [list \
|
||||
CONFIG.DATA_WIDTH {256} \
|
||||
CONFIG.ID_WIDTH {2} \
|
||||
CONFIG.M00_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_READ_ISSUING {8} \
|
||||
CONFIG.M00_WRITE_ISSUING {8} \
|
||||
CONFIG.M01_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M01_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_READ_ISSUING {8} \
|
||||
CONFIG.M01_WRITE_ISSUING {8} \
|
||||
CONFIG.M02_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M02_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_READ_ISSUING {8} \
|
||||
CONFIG.M02_WRITE_ISSUING {8} \
|
||||
CONFIG.M03_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M03_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_READ_ISSUING {8} \
|
||||
CONFIG.M03_WRITE_ISSUING {8} \
|
||||
CONFIG.M04_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M04_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_READ_ISSUING {8} \
|
||||
CONFIG.M04_WRITE_ISSUING {8} \
|
||||
CONFIG.M05_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M05_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_READ_ISSUING {8} \
|
||||
CONFIG.M05_WRITE_ISSUING {8} \
|
||||
CONFIG.M06_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M06_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_READ_ISSUING {8} \
|
||||
CONFIG.M06_WRITE_ISSUING {8} \
|
||||
CONFIG.M07_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M07_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_READ_ISSUING {8} \
|
||||
CONFIG.M07_WRITE_ISSUING {8} \
|
||||
CONFIG.M08_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M08_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_READ_ISSUING {8} \
|
||||
CONFIG.M08_WRITE_ISSUING {8} \
|
||||
CONFIG.M09_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M09_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_READ_ISSUING {8} \
|
||||
CONFIG.M09_WRITE_ISSUING {8} \
|
||||
CONFIG.M10_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M10_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_READ_ISSUING {8} \
|
||||
CONFIG.M10_WRITE_ISSUING {8} \
|
||||
CONFIG.M11_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M11_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_READ_ISSUING {8} \
|
||||
CONFIG.M11_WRITE_ISSUING {8} \
|
||||
CONFIG.M12_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M12_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_READ_ISSUING {8} \
|
||||
CONFIG.M12_WRITE_ISSUING {8} \
|
||||
CONFIG.M13_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M13_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_READ_ISSUING {8} \
|
||||
CONFIG.M13_WRITE_ISSUING {8} \
|
||||
CONFIG.M14_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M14_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_READ_ISSUING {8} \
|
||||
CONFIG.M14_WRITE_ISSUING {8} \
|
||||
CONFIG.M15_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M15_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_READ_ISSUING {8} \
|
||||
CONFIG.M15_WRITE_ISSUING {8} \
|
||||
CONFIG.NUM_MI {1} \
|
||||
CONFIG.NUM_SI {4} \
|
||||
CONFIG.S00_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S00_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S01_BASE_ID {0x00000001} \
|
||||
CONFIG.S01_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S01_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S02_BASE_ID {0x00000002} \
|
||||
CONFIG.S02_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S02_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S03_BASE_ID {0x00000003} \
|
||||
CONFIG.S03_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S03_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S04_BASE_ID {0x00000004} \
|
||||
CONFIG.S04_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S04_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S05_BASE_ID {0x00000005} \
|
||||
CONFIG.S05_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S05_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S06_BASE_ID {0x00000006} \
|
||||
CONFIG.S06_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S06_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S07_BASE_ID {0x00000007} \
|
||||
CONFIG.S07_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S07_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S08_BASE_ID {0x00000008} \
|
||||
CONFIG.S08_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S08_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S09_BASE_ID {0x00000009} \
|
||||
CONFIG.S09_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S09_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S10_BASE_ID {0x0000000a} \
|
||||
CONFIG.S10_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S10_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S11_BASE_ID {0x0000000b} \
|
||||
CONFIG.S11_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S11_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S12_BASE_ID {0x0000000c} \
|
||||
CONFIG.S12_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S12_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S13_BASE_ID {0x0000000d} \
|
||||
CONFIG.S13_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S13_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S14_BASE_ID {0x0000000e} \
|
||||
CONFIG.S14_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S14_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.S15_BASE_ID {0x0000000f} \
|
||||
CONFIG.S15_READ_ACCEPTANCE {4} \
|
||||
CONFIG.S15_WRITE_ACCEPTANCE {4} \
|
||||
CONFIG.STRATEGY {2} \
|
||||
] $xbar
|
||||
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports S00_AXI] [get_bd_intf_pins s00_rs_0/S_AXI]
|
||||
connect_bd_intf_net -intf_net S01_AXI_1 [get_bd_intf_ports S01_AXI] [get_bd_intf_pins s01_rs_0/S_AXI]
|
||||
@ -533,16 +888,52 @@ proc create_root_design { parentCell } {
|
||||
connect_bd_intf_net -intf_net xbar_M00_AXI [get_bd_intf_pins m00_rs/S_AXI] [get_bd_intf_pins xbar/M00_AXI]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net M00_AXI_ACLK_1 [get_bd_ports M00_AXI_ACLK] [get_bd_pins m00_rs/aclk] [get_bd_pins s00_rs_1/aclk] [get_bd_pins s00_width_conv/m_axi_aclk] [get_bd_pins s01_rs_1/aclk] [get_bd_pins s01_width_conv/m_axi_aclk] [get_bd_pins s02_rs_1/aclk] [get_bd_pins s02_width_conv/m_axi_aclk] [get_bd_pins s03_rs_1/aclk] [get_bd_pins s03_width_conv/m_axi_aclk] [get_bd_pins xbar/aclk]
|
||||
connect_bd_net -net M00_AXI_ARESETN_1 [get_bd_ports M00_AXI_ARESETN] [get_bd_pins m00_rs/aresetn] [get_bd_pins s00_rs_1/aresetn] [get_bd_pins s00_width_conv/m_axi_aresetn] [get_bd_pins s01_rs_1/aresetn] [get_bd_pins s01_width_conv/m_axi_aresetn] [get_bd_pins s02_rs_1/aresetn] [get_bd_pins s02_width_conv/m_axi_aresetn] [get_bd_pins s03_rs_1/aresetn] [get_bd_pins s03_width_conv/m_axi_aresetn] [get_bd_pins xbar/aresetn]
|
||||
connect_bd_net -net S00_AXI_ACLK_1 [get_bd_ports S00_AXI_ACLK] [get_bd_pins s00_rs_0/aclk] [get_bd_pins s00_width_conv/s_axi_aclk]
|
||||
connect_bd_net -net S00_AXI_ARESETN_1 [get_bd_ports S00_AXI_ARESETN] [get_bd_pins s00_rs_0/aresetn] [get_bd_pins s00_width_conv/s_axi_aresetn]
|
||||
connect_bd_net -net S01_AXI_ACLK_1 [get_bd_ports S01_AXI_ACLK] [get_bd_pins s01_rs_0/aclk] [get_bd_pins s01_width_conv/s_axi_aclk]
|
||||
connect_bd_net -net S01_AXI_ARESETN_1 [get_bd_ports S01_AXI_ARESETN] [get_bd_pins s01_rs_0/aresetn] [get_bd_pins s01_width_conv/s_axi_aresetn]
|
||||
connect_bd_net -net S02_AXI_ACLK_1 [get_bd_ports S02_AXI_ACLK] [get_bd_pins s02_rs_0/aclk] [get_bd_pins s02_width_conv/s_axi_aclk]
|
||||
connect_bd_net -net S02_AXI_ARESETN_1 [get_bd_ports S02_AXI_ARESETN] [get_bd_pins s02_rs_0/aresetn] [get_bd_pins s02_width_conv/s_axi_aresetn]
|
||||
connect_bd_net -net S03_AXI_ACLK_1 [get_bd_ports S03_AXI_ACLK] [get_bd_pins s03_rs_0/aclk] [get_bd_pins s03_width_conv/s_axi_aclk]
|
||||
connect_bd_net -net S03_AXI_ARESETN_1 [get_bd_ports S03_AXI_ARESETN] [get_bd_pins s03_rs_0/aresetn] [get_bd_pins s03_width_conv/s_axi_aresetn]
|
||||
connect_bd_net -net M00_AXI_ACLK_1 [get_bd_ports M00_AXI_ACLK] \
|
||||
[get_bd_pins m00_rs/aclk] \
|
||||
[get_bd_pins s00_rs_1/aclk] \
|
||||
[get_bd_pins s00_width_conv/m_axi_aclk] \
|
||||
[get_bd_pins s01_rs_1/aclk] \
|
||||
[get_bd_pins s01_width_conv/m_axi_aclk] \
|
||||
[get_bd_pins s02_rs_1/aclk] \
|
||||
[get_bd_pins s02_width_conv/m_axi_aclk] \
|
||||
[get_bd_pins s03_rs_1/aclk] \
|
||||
[get_bd_pins s03_width_conv/m_axi_aclk] \
|
||||
[get_bd_pins xbar/aclk]
|
||||
connect_bd_net -net M00_AXI_ARESETN_1 [get_bd_ports M00_AXI_ARESETN] \
|
||||
[get_bd_pins m00_rs/aresetn] \
|
||||
[get_bd_pins s00_rs_1/aresetn] \
|
||||
[get_bd_pins s00_width_conv/m_axi_aresetn] \
|
||||
[get_bd_pins s01_rs_1/aresetn] \
|
||||
[get_bd_pins s01_width_conv/m_axi_aresetn] \
|
||||
[get_bd_pins s02_rs_1/aresetn] \
|
||||
[get_bd_pins s02_width_conv/m_axi_aresetn] \
|
||||
[get_bd_pins s03_rs_1/aresetn] \
|
||||
[get_bd_pins s03_width_conv/m_axi_aresetn] \
|
||||
[get_bd_pins xbar/aresetn]
|
||||
connect_bd_net -net S00_AXI_ACLK_1 [get_bd_ports S00_AXI_ACLK] \
|
||||
[get_bd_pins s00_rs_0/aclk] \
|
||||
[get_bd_pins s00_width_conv/s_axi_aclk]
|
||||
connect_bd_net -net S00_AXI_ARESETN_1 [get_bd_ports S00_AXI_ARESETN] \
|
||||
[get_bd_pins s00_rs_0/aresetn] \
|
||||
[get_bd_pins s00_width_conv/s_axi_aresetn]
|
||||
connect_bd_net -net S01_AXI_ACLK_1 [get_bd_ports S01_AXI_ACLK] \
|
||||
[get_bd_pins s01_rs_0/aclk] \
|
||||
[get_bd_pins s01_width_conv/s_axi_aclk]
|
||||
connect_bd_net -net S01_AXI_ARESETN_1 [get_bd_ports S01_AXI_ARESETN] \
|
||||
[get_bd_pins s01_rs_0/aresetn] \
|
||||
[get_bd_pins s01_width_conv/s_axi_aresetn]
|
||||
connect_bd_net -net S02_AXI_ACLK_1 [get_bd_ports S02_AXI_ACLK] \
|
||||
[get_bd_pins s02_rs_0/aclk] \
|
||||
[get_bd_pins s02_width_conv/s_axi_aclk]
|
||||
connect_bd_net -net S02_AXI_ARESETN_1 [get_bd_ports S02_AXI_ARESETN] \
|
||||
[get_bd_pins s02_rs_0/aresetn] \
|
||||
[get_bd_pins s02_width_conv/s_axi_aresetn]
|
||||
connect_bd_net -net S03_AXI_ACLK_1 [get_bd_ports S03_AXI_ACLK] \
|
||||
[get_bd_pins s03_rs_0/aclk] \
|
||||
[get_bd_pins s03_width_conv/s_axi_aclk]
|
||||
connect_bd_net -net S03_AXI_ARESETN_1 [get_bd_ports S03_AXI_ARESETN] \
|
||||
[get_bd_pins s03_rs_0/aresetn] \
|
||||
[get_bd_pins s03_width_conv/s_axi_aresetn]
|
||||
|
||||
# Create address segments
|
||||
assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces S00_AXI] [get_bd_addr_segs M00_AXI/Reg] -force
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,7 +1,7 @@
|
||||
#!/bin/bash
|
||||
|
||||
VIVADO_VER=2021.1
|
||||
VIVADO_VER_FULL=2021.1_AR76780
|
||||
VIVADO_VER=2025.2
|
||||
VIVADO_VER_FULL=2025.2
|
||||
DISPLAY_NAME="USRP-B310"
|
||||
REPO_BASE_PATH=$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user