From f3d6cd6c01b10c882415c064642c864b03101ecf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Max=20K=C3=B6hler?= Date: Tue, 15 Sep 2026 18:03:39 +0200 Subject: [PATCH] fpga: b300: Upgrade to Vivado 2025.2 --- fpga/usrp3/top/b300/b310.sv | 10 +- .../axi_intercon_2x64_256_bd.tcl | 522 +- .../axi_intercon_4x64_256_bd.tcl | 645 ++- .../top/b300/ip/bus_clk_gen/bus_clk_gen.xci | 1470 +++--- .../top/b300/ip/ddr3_32bit/ddr3_32bit.xci | 4611 ++++++----------- .../b300/ip/fifo_32bit_4k/fifo_32bit_4k.xci | 1039 ++-- .../b300/ip/radio_clk_gen/radio_clk_gen.xci | 1498 +++--- .../top/b300/ip/ref_clk_pll/ref_clk_pll.xci | 1415 +++-- fpga/usrp3/top/b300/setupenv.sh | 4 +- 9 files changed, 5234 insertions(+), 5980 deletions(-) diff --git a/fpga/usrp3/top/b300/b310.sv b/fpga/usrp3/top/b300/b310.sv index d962a14bd..32ea370da 100644 --- a/fpga/usrp3/top/b300/b310.sv +++ b/fpga/usrp3/top/b300/b310.sv @@ -238,12 +238,19 @@ module b310 .clk_in1 (bus_clk_in) //input wire ); + logic dev_clk; logic radio_clk; logic radio_clk_2x; logic radio_clk_gen_locked; logic radio_clk_shifted; logic radio_clk_gen_rst; + IBUFDS IBUFDS_ref_clk ( + .O(dev_clk), + .I(DEVCLK_P), + .IB(DEVCLK_N) + ); + radio_clk_gen radio_clk_gen_i ( .clk_out1 (radio_clk), //output wire .clk_out2 (radio_clk_2x), //output wire @@ -251,8 +258,7 @@ module b310 .clk_out4 (radio_clk_shifted), //output wire .reset (radio_clk_gen_rst), //input wire .locked (radio_clk_gen_locked), //output wire - .clk_in1_p(DEVCLK_P), //input wire - .clk_in1_n(DEVCLK_N) //input wire + .clk_in1 (dev_clk) //input wire ); diff --git a/fpga/usrp3/top/b300/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.tcl b/fpga/usrp3/top/b300/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.tcl index 0e46f66f6..5a11c340e 100644 --- a/fpga/usrp3/top/b300/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.tcl +++ b/fpga/usrp3/top/b300/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.tcl @@ -20,12 +20,18 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2021.1 +set scripts_vivado_version 2025.2 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."} + + } else { + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + } return 1 } @@ -284,96 +290,438 @@ proc create_root_design { parentCell } { # Create instance: m00_rs, and set properties set m00_rs [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 m00_rs ] - set_property -dict [ list \ - CONFIG.REG_AR {1} \ - CONFIG.REG_AW {1} \ - CONFIG.REG_B {1} \ - ] $m00_rs + set_property -dict [list \ + CONFIG.REG_AR {7} \ + CONFIG.REG_AW {7} \ + CONFIG.REG_B {7} \ + ] $m00_rs + # Create instance: s00_rs_0, and set properties set s00_rs_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s00_rs_0 ] - set_property -dict [ list \ - CONFIG.REG_AR {1} \ - CONFIG.REG_AW {1} \ - CONFIG.REG_B {1} \ - CONFIG.REG_R {1} \ - CONFIG.REG_W {1} \ - ] $s00_rs_0 + set_property -dict [list \ + CONFIG.REG_AR {7} \ + CONFIG.REG_AW {7} \ + CONFIG.REG_B {7} \ + CONFIG.REG_R {1} \ + CONFIG.REG_W {1} \ + ] $s00_rs_0 + # Create instance: s00_rs_1, and set properties set s00_rs_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s00_rs_1 ] - set_property -dict [ list \ - CONFIG.REG_AR {1} \ - CONFIG.REG_AW {1} \ - CONFIG.REG_B {1} \ - CONFIG.REG_R {1} \ - CONFIG.REG_W {1} \ - ] $s00_rs_1 + set_property -dict [list \ + CONFIG.REG_AR {7} \ + CONFIG.REG_AW {7} \ + CONFIG.REG_B {7} \ + CONFIG.REG_R {1} \ + CONFIG.REG_W {1} \ + ] $s00_rs_1 + # Create instance: s00_width_conv, and set properties set s00_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s00_width_conv ] - set_property -dict [ list \ - CONFIG.ACLK_ASYNC {1} \ - CONFIG.FIFO_MODE {2} \ - CONFIG.MI_DATA_WIDTH {256} \ - CONFIG.SI_DATA_WIDTH {64} \ - CONFIG.SYNCHRONIZATION_STAGES {2} \ - ] $s00_width_conv + set_property -dict [list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.MI_DATA_WIDTH {256} \ + CONFIG.SI_DATA_WIDTH {64} \ + CONFIG.SYNCHRONIZATION_STAGES {2} \ + ] $s00_width_conv + # Create instance: s01_rs_0, and set properties set s01_rs_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s01_rs_0 ] - set_property -dict [ list \ - CONFIG.REG_AR {1} \ - CONFIG.REG_AW {1} \ - CONFIG.REG_B {1} \ - CONFIG.REG_R {1} \ - CONFIG.REG_W {1} \ - ] $s01_rs_0 + set_property -dict [list \ + CONFIG.REG_AR {7} \ + CONFIG.REG_AW {7} \ + CONFIG.REG_B {7} \ + CONFIG.REG_R {1} \ + CONFIG.REG_W {1} \ + ] $s01_rs_0 + # Create instance: s01_rs_1, and set properties set s01_rs_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s01_rs_1 ] - set_property -dict [ list \ - CONFIG.REG_AR {1} \ - CONFIG.REG_AW {1} \ - CONFIG.REG_B {1} \ - CONFIG.REG_R {1} \ - CONFIG.REG_W {1} \ - ] $s01_rs_1 + set_property -dict [list \ + CONFIG.REG_AR {7} \ + CONFIG.REG_AW {7} \ + CONFIG.REG_B {7} \ + CONFIG.REG_R {1} \ + CONFIG.REG_W {1} \ + ] $s01_rs_1 + # Create instance: s01_width_conv, and set properties set s01_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s01_width_conv ] - set_property -dict [ list \ - CONFIG.ACLK_ASYNC {1} \ - CONFIG.FIFO_MODE {2} \ - CONFIG.MI_DATA_WIDTH {256} \ - CONFIG.SI_DATA_WIDTH {64} \ - CONFIG.SYNCHRONIZATION_STAGES {2} \ - ] $s01_width_conv + set_property -dict [list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.MI_DATA_WIDTH {256} \ + CONFIG.SI_DATA_WIDTH {64} \ + CONFIG.SYNCHRONIZATION_STAGES {2} \ + ] $s01_width_conv + # Create instance: xbar, and set properties set xbar [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 xbar ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {256} \ - CONFIG.ID_WIDTH {1} \ - CONFIG.NUM_MI {1} \ - CONFIG.NUM_SI {2} \ - CONFIG.S01_BASE_ID {0x00000001} \ - CONFIG.S02_BASE_ID {0x00000002} \ - CONFIG.S03_BASE_ID {0x00000003} \ - CONFIG.S04_BASE_ID {0x00000004} \ - CONFIG.S05_BASE_ID {0x00000005} \ - CONFIG.S06_BASE_ID {0x00000006} \ - CONFIG.S07_BASE_ID {0x00000007} \ - CONFIG.S08_BASE_ID {0x00000008} \ - CONFIG.S09_BASE_ID {0x00000009} \ - CONFIG.S10_BASE_ID {0x0000000a} \ - CONFIG.S11_BASE_ID {0x0000000b} \ - CONFIG.S12_BASE_ID {0x0000000c} \ - CONFIG.S13_BASE_ID {0x0000000d} \ - CONFIG.S14_BASE_ID {0x0000000e} \ - CONFIG.S15_BASE_ID {0x0000000f} \ - CONFIG.STRATEGY {2} \ - ] $xbar + set_property -dict [list \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.M00_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_READ_ISSUING {8} \ + CONFIG.M00_WRITE_ISSUING {8} \ + CONFIG.M01_A00_ADDR_WIDTH {0} \ + CONFIG.M01_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_READ_ISSUING {8} \ + CONFIG.M01_WRITE_ISSUING {8} \ + CONFIG.M02_A00_ADDR_WIDTH {0} \ + CONFIG.M02_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_READ_ISSUING {8} \ + CONFIG.M02_WRITE_ISSUING {8} \ + CONFIG.M03_A00_ADDR_WIDTH {0} \ + CONFIG.M03_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_READ_ISSUING {8} \ + CONFIG.M03_WRITE_ISSUING {8} \ + CONFIG.M04_A00_ADDR_WIDTH {0} \ + CONFIG.M04_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_READ_ISSUING {8} \ + CONFIG.M04_WRITE_ISSUING {8} \ + CONFIG.M05_A00_ADDR_WIDTH {0} \ + CONFIG.M05_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_READ_ISSUING {8} \ + CONFIG.M05_WRITE_ISSUING {8} \ + CONFIG.M06_A00_ADDR_WIDTH {0} \ + CONFIG.M06_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_READ_ISSUING {8} \ + CONFIG.M06_WRITE_ISSUING {8} \ + CONFIG.M07_A00_ADDR_WIDTH {0} \ + CONFIG.M07_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_READ_ISSUING {8} \ + CONFIG.M07_WRITE_ISSUING {8} \ + CONFIG.M08_A00_ADDR_WIDTH {0} \ + CONFIG.M08_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_READ_ISSUING {8} \ + CONFIG.M08_WRITE_ISSUING {8} \ + CONFIG.M09_A00_ADDR_WIDTH {0} \ + CONFIG.M09_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_READ_ISSUING {8} \ + CONFIG.M09_WRITE_ISSUING {8} \ + CONFIG.M10_A00_ADDR_WIDTH {0} \ + CONFIG.M10_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_READ_ISSUING {8} \ + CONFIG.M10_WRITE_ISSUING {8} \ + CONFIG.M11_A00_ADDR_WIDTH {0} \ + CONFIG.M11_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_READ_ISSUING {8} \ + CONFIG.M11_WRITE_ISSUING {8} \ + CONFIG.M12_A00_ADDR_WIDTH {0} \ + CONFIG.M12_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_READ_ISSUING {8} \ + CONFIG.M12_WRITE_ISSUING {8} \ + CONFIG.M13_A00_ADDR_WIDTH {0} \ + CONFIG.M13_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_READ_ISSUING {8} \ + CONFIG.M13_WRITE_ISSUING {8} \ + CONFIG.M14_A00_ADDR_WIDTH {0} \ + CONFIG.M14_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_READ_ISSUING {8} \ + CONFIG.M14_WRITE_ISSUING {8} \ + CONFIG.M15_A00_ADDR_WIDTH {0} \ + CONFIG.M15_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_READ_ISSUING {8} \ + CONFIG.M15_WRITE_ISSUING {8} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {2} \ + CONFIG.S00_READ_ACCEPTANCE {4} \ + CONFIG.S00_WRITE_ACCEPTANCE {4} \ + CONFIG.S01_BASE_ID {0x00000001} \ + CONFIG.S01_READ_ACCEPTANCE {4} \ + CONFIG.S01_WRITE_ACCEPTANCE {4} \ + CONFIG.S02_BASE_ID {0x00000002} \ + CONFIG.S02_READ_ACCEPTANCE {4} \ + CONFIG.S02_WRITE_ACCEPTANCE {4} \ + CONFIG.S03_BASE_ID {0x00000003} \ + CONFIG.S03_READ_ACCEPTANCE {4} \ + CONFIG.S03_WRITE_ACCEPTANCE {4} \ + CONFIG.S04_BASE_ID {0x00000004} \ + CONFIG.S04_READ_ACCEPTANCE {4} \ + CONFIG.S04_WRITE_ACCEPTANCE {4} \ + CONFIG.S05_BASE_ID {0x00000005} \ + CONFIG.S05_READ_ACCEPTANCE {4} \ + CONFIG.S05_WRITE_ACCEPTANCE {4} \ + CONFIG.S06_BASE_ID {0x00000006} \ + CONFIG.S06_READ_ACCEPTANCE {4} \ + CONFIG.S06_WRITE_ACCEPTANCE {4} \ + CONFIG.S07_BASE_ID {0x00000007} \ + CONFIG.S07_READ_ACCEPTANCE {4} \ + CONFIG.S07_WRITE_ACCEPTANCE {4} \ + CONFIG.S08_BASE_ID {0x00000008} \ + CONFIG.S08_READ_ACCEPTANCE {4} \ + CONFIG.S08_WRITE_ACCEPTANCE {4} \ + CONFIG.S09_BASE_ID {0x00000009} \ + CONFIG.S09_READ_ACCEPTANCE {4} \ + CONFIG.S09_WRITE_ACCEPTANCE {4} \ + CONFIG.S10_BASE_ID {0x0000000a} \ + CONFIG.S10_READ_ACCEPTANCE {4} \ + CONFIG.S10_WRITE_ACCEPTANCE {4} \ + CONFIG.S11_BASE_ID {0x0000000b} \ + CONFIG.S11_READ_ACCEPTANCE {4} \ + CONFIG.S11_WRITE_ACCEPTANCE {4} \ + CONFIG.S12_BASE_ID {0x0000000c} \ + CONFIG.S12_READ_ACCEPTANCE {4} \ + CONFIG.S12_WRITE_ACCEPTANCE {4} \ + CONFIG.S13_BASE_ID {0x0000000d} \ + CONFIG.S13_READ_ACCEPTANCE {4} \ + CONFIG.S13_WRITE_ACCEPTANCE {4} \ + CONFIG.S14_BASE_ID {0x0000000e} \ + CONFIG.S14_READ_ACCEPTANCE {4} \ + CONFIG.S14_WRITE_ACCEPTANCE {4} \ + CONFIG.S15_BASE_ID {0x0000000f} \ + CONFIG.S15_READ_ACCEPTANCE {4} \ + CONFIG.S15_WRITE_ACCEPTANCE {4} \ + CONFIG.STRATEGY {2} \ + ] $xbar + # Create interface connections connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports S00_AXI] [get_bd_intf_pins s00_rs_0/S_AXI] @@ -388,12 +736,32 @@ proc create_root_design { parentCell } { connect_bd_intf_net -intf_net xbar_M00_AXI [get_bd_intf_pins m00_rs/S_AXI] [get_bd_intf_pins xbar/M00_AXI] # Create port connections - connect_bd_net -net M00_AXI_ACLK_1 [get_bd_ports M00_AXI_ACLK] [get_bd_pins m00_rs/aclk] [get_bd_pins s00_rs_1/aclk] [get_bd_pins s00_width_conv/m_axi_aclk] [get_bd_pins s01_rs_1/aclk] [get_bd_pins s01_width_conv/m_axi_aclk] [get_bd_pins xbar/aclk] - connect_bd_net -net M00_AXI_ARESETN_1 [get_bd_ports M00_AXI_ARESETN] [get_bd_pins m00_rs/aresetn] [get_bd_pins s00_rs_1/aresetn] [get_bd_pins s00_width_conv/m_axi_aresetn] [get_bd_pins s01_rs_1/aresetn] [get_bd_pins s01_width_conv/m_axi_aresetn] [get_bd_pins xbar/aresetn] - connect_bd_net -net S00_AXI_ACLK_1 [get_bd_ports S00_AXI_ACLK] [get_bd_pins s00_rs_0/aclk] [get_bd_pins s00_width_conv/s_axi_aclk] - connect_bd_net -net S00_AXI_ARESETN_1 [get_bd_ports S00_AXI_ARESETN] [get_bd_pins s00_rs_0/aresetn] [get_bd_pins s00_width_conv/s_axi_aresetn] - connect_bd_net -net S01_AXI_ACLK_1 [get_bd_ports S01_AXI_ACLK] [get_bd_pins s01_rs_0/aclk] [get_bd_pins s01_width_conv/s_axi_aclk] - connect_bd_net -net S01_AXI_ARESETN_1 [get_bd_ports S01_AXI_ARESETN] [get_bd_pins s01_rs_0/aresetn] [get_bd_pins s01_width_conv/s_axi_aresetn] + connect_bd_net -net M00_AXI_ACLK_1 [get_bd_ports M00_AXI_ACLK] \ + [get_bd_pins m00_rs/aclk] \ + [get_bd_pins s00_rs_1/aclk] \ + [get_bd_pins s00_width_conv/m_axi_aclk] \ + [get_bd_pins s01_rs_1/aclk] \ + [get_bd_pins s01_width_conv/m_axi_aclk] \ + [get_bd_pins xbar/aclk] + connect_bd_net -net M00_AXI_ARESETN_1 [get_bd_ports M00_AXI_ARESETN] \ + [get_bd_pins m00_rs/aresetn] \ + [get_bd_pins s00_rs_1/aresetn] \ + [get_bd_pins s00_width_conv/m_axi_aresetn] \ + [get_bd_pins s01_rs_1/aresetn] \ + [get_bd_pins s01_width_conv/m_axi_aresetn] \ + [get_bd_pins xbar/aresetn] + connect_bd_net -net S00_AXI_ACLK_1 [get_bd_ports S00_AXI_ACLK] \ + [get_bd_pins s00_rs_0/aclk] \ + [get_bd_pins s00_width_conv/s_axi_aclk] + connect_bd_net -net S00_AXI_ARESETN_1 [get_bd_ports S00_AXI_ARESETN] \ + [get_bd_pins s00_rs_0/aresetn] \ + [get_bd_pins s00_width_conv/s_axi_aresetn] + connect_bd_net -net S01_AXI_ACLK_1 [get_bd_ports S01_AXI_ACLK] \ + [get_bd_pins s01_rs_0/aclk] \ + [get_bd_pins s01_width_conv/s_axi_aclk] + connect_bd_net -net S01_AXI_ARESETN_1 [get_bd_ports S01_AXI_ARESETN] \ + [get_bd_pins s01_rs_0/aresetn] \ + [get_bd_pins s01_width_conv/s_axi_aresetn] # Create address segments assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces S00_AXI] [get_bd_addr_segs M00_AXI/Reg] -force diff --git a/fpga/usrp3/top/b300/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.tcl b/fpga/usrp3/top/b300/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.tcl index e1775aa46..28355a2c3 100644 --- a/fpga/usrp3/top/b300/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.tcl +++ b/fpga/usrp3/top/b300/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.tcl @@ -20,12 +20,18 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2021.1 +set scripts_vivado_version 2025.2 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."} + + } else { + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + } return 1 } @@ -193,6 +199,7 @@ proc create_root_design { parentCell } { set_property -dict [ list \ CONFIG.ADDR_WIDTH {32} \ CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {1000000000} \ CONFIG.NUM_READ_OUTSTANDING {2} \ CONFIG.NUM_WRITE_OUTSTANDING {2} \ CONFIG.PROTOCOL {AXI4} \ @@ -205,7 +212,7 @@ proc create_root_design { parentCell } { CONFIG.AWUSER_WIDTH {0} \ CONFIG.BUSER_WIDTH {0} \ CONFIG.DATA_WIDTH {64} \ - CONFIG.FREQ_HZ {1000000000} \ + CONFIG.FREQ_HZ {2000000000} \ CONFIG.HAS_BRESP {1} \ CONFIG.HAS_BURST {1} \ CONFIG.HAS_CACHE {1} \ @@ -237,7 +244,7 @@ proc create_root_design { parentCell } { CONFIG.AWUSER_WIDTH {0} \ CONFIG.BUSER_WIDTH {0} \ CONFIG.DATA_WIDTH {64} \ - CONFIG.FREQ_HZ {1000000000} \ + CONFIG.FREQ_HZ {2000000000} \ CONFIG.HAS_BRESP {1} \ CONFIG.HAS_BURST {1} \ CONFIG.HAS_CACHE {1} \ @@ -269,7 +276,7 @@ proc create_root_design { parentCell } { CONFIG.AWUSER_WIDTH {0} \ CONFIG.BUSER_WIDTH {0} \ CONFIG.DATA_WIDTH {64} \ - CONFIG.FREQ_HZ {1000000000} \ + CONFIG.FREQ_HZ {2000000000} \ CONFIG.HAS_BRESP {1} \ CONFIG.HAS_BURST {1} \ CONFIG.HAS_CACHE {1} \ @@ -301,7 +308,7 @@ proc create_root_design { parentCell } { CONFIG.AWUSER_WIDTH {0} \ CONFIG.BUSER_WIDTH {0} \ CONFIG.DATA_WIDTH {64} \ - CONFIG.FREQ_HZ {1000000000} \ + CONFIG.FREQ_HZ {2000000000} \ CONFIG.HAS_BRESP {1} \ CONFIG.HAS_BURST {1} \ CONFIG.HAS_CACHE {1} \ @@ -361,156 +368,504 @@ proc create_root_design { parentCell } { # Create instance: m00_rs, and set properties set m00_rs [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 m00_rs ] - set_property -dict [ list \ - CONFIG.REG_AR {1} \ - CONFIG.REG_AW {1} \ - CONFIG.REG_B {1} \ - ] $m00_rs + set_property -dict [list \ + CONFIG.REG_AR {7} \ + CONFIG.REG_AW {7} \ + CONFIG.REG_B {7} \ + ] $m00_rs + # Create instance: s00_rs_0, and set properties set s00_rs_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s00_rs_0 ] - set_property -dict [ list \ - CONFIG.REG_AR {1} \ - CONFIG.REG_AW {1} \ - CONFIG.REG_B {1} \ - CONFIG.REG_R {1} \ - CONFIG.REG_W {1} \ - ] $s00_rs_0 + set_property -dict [list \ + CONFIG.REG_AR {7} \ + CONFIG.REG_AW {7} \ + CONFIG.REG_B {7} \ + CONFIG.REG_R {1} \ + CONFIG.REG_W {1} \ + ] $s00_rs_0 + # Create instance: s00_rs_1, and set properties set s00_rs_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s00_rs_1 ] - set_property -dict [ list \ - CONFIG.REG_AR {1} \ - CONFIG.REG_AW {1} \ - CONFIG.REG_B {1} \ - CONFIG.REG_R {1} \ - CONFIG.REG_W {1} \ - ] $s00_rs_1 + set_property -dict [list \ + CONFIG.REG_AR {7} \ + CONFIG.REG_AW {7} \ + CONFIG.REG_B {7} \ + CONFIG.REG_R {1} \ + CONFIG.REG_W {1} \ + ] $s00_rs_1 + # Create instance: s00_width_conv, and set properties set s00_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s00_width_conv ] - set_property -dict [ list \ - CONFIG.ACLK_ASYNC {1} \ - CONFIG.FIFO_MODE {2} \ - CONFIG.MI_DATA_WIDTH {256} \ - CONFIG.SI_DATA_WIDTH {64} \ - CONFIG.SYNCHRONIZATION_STAGES {2} \ - ] $s00_width_conv + set_property -dict [list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.MI_DATA_WIDTH {256} \ + CONFIG.SI_DATA_WIDTH {64} \ + CONFIG.SYNCHRONIZATION_STAGES {2} \ + ] $s00_width_conv + # Create instance: s01_rs_0, and set properties set s01_rs_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s01_rs_0 ] - set_property -dict [ list \ - CONFIG.REG_AR {1} \ - CONFIG.REG_AW {1} \ - CONFIG.REG_B {1} \ - CONFIG.REG_R {1} \ - CONFIG.REG_W {1} \ - ] $s01_rs_0 + set_property -dict [list \ + CONFIG.REG_AR {7} \ + CONFIG.REG_AW {7} \ + CONFIG.REG_B {7} \ + CONFIG.REG_R {1} \ + CONFIG.REG_W {1} \ + ] $s01_rs_0 + # Create instance: s01_rs_1, and set properties set s01_rs_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s01_rs_1 ] - set_property -dict [ list \ - CONFIG.REG_AR {1} \ - CONFIG.REG_AW {1} \ - CONFIG.REG_B {1} \ - CONFIG.REG_R {1} \ - CONFIG.REG_W {1} \ - ] $s01_rs_1 + set_property -dict [list \ + CONFIG.REG_AR {7} \ + CONFIG.REG_AW {7} \ + CONFIG.REG_B {7} \ + CONFIG.REG_R {1} \ + CONFIG.REG_W {1} \ + ] $s01_rs_1 + # Create instance: s01_width_conv, and set properties set s01_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s01_width_conv ] - set_property -dict [ list \ - CONFIG.ACLK_ASYNC {1} \ - CONFIG.FIFO_MODE {2} \ - CONFIG.MI_DATA_WIDTH {256} \ - CONFIG.SI_DATA_WIDTH {64} \ - CONFIG.SYNCHRONIZATION_STAGES {2} \ - ] $s01_width_conv + set_property -dict [list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.MI_DATA_WIDTH {256} \ + CONFIG.SI_DATA_WIDTH {64} \ + CONFIG.SYNCHRONIZATION_STAGES {2} \ + ] $s01_width_conv + # Create instance: s02_rs_0, and set properties set s02_rs_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s02_rs_0 ] - set_property -dict [ list \ - CONFIG.REG_AR {1} \ - CONFIG.REG_AW {1} \ - CONFIG.REG_B {1} \ - CONFIG.REG_R {1} \ - CONFIG.REG_W {1} \ - ] $s02_rs_0 + set_property -dict [list \ + CONFIG.REG_AR {7} \ + CONFIG.REG_AW {7} \ + CONFIG.REG_B {7} \ + CONFIG.REG_R {1} \ + CONFIG.REG_W {1} \ + ] $s02_rs_0 + # Create instance: s02_rs_1, and set properties set s02_rs_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s02_rs_1 ] - set_property -dict [ list \ - CONFIG.REG_AR {1} \ - CONFIG.REG_AW {1} \ - CONFIG.REG_B {1} \ - CONFIG.REG_R {1} \ - CONFIG.REG_W {1} \ - ] $s02_rs_1 + set_property -dict [list \ + CONFIG.REG_AR {7} \ + CONFIG.REG_AW {7} \ + CONFIG.REG_B {7} \ + CONFIG.REG_R {1} \ + CONFIG.REG_W {1} \ + ] $s02_rs_1 + # Create instance: s02_width_conv, and set properties set s02_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s02_width_conv ] - set_property -dict [ list \ - CONFIG.ACLK_ASYNC {1} \ - CONFIG.FIFO_MODE {2} \ - CONFIG.MI_DATA_WIDTH {256} \ - CONFIG.SI_DATA_WIDTH {64} \ - CONFIG.SYNCHRONIZATION_STAGES {2} \ - ] $s02_width_conv + set_property -dict [list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.MI_DATA_WIDTH {256} \ + CONFIG.SI_DATA_WIDTH {64} \ + CONFIG.SYNCHRONIZATION_STAGES {2} \ + ] $s02_width_conv + # Create instance: s03_rs_0, and set properties set s03_rs_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s03_rs_0 ] - set_property -dict [ list \ - CONFIG.REG_AR {1} \ - CONFIG.REG_AW {1} \ - CONFIG.REG_B {1} \ - CONFIG.REG_R {1} \ - CONFIG.REG_W {1} \ - ] $s03_rs_0 + set_property -dict [list \ + CONFIG.REG_AR {7} \ + CONFIG.REG_AW {7} \ + CONFIG.REG_B {7} \ + CONFIG.REG_R {1} \ + CONFIG.REG_W {1} \ + ] $s03_rs_0 + # Create instance: s03_rs_1, and set properties set s03_rs_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 s03_rs_1 ] - set_property -dict [ list \ - CONFIG.REG_AR {1} \ - CONFIG.REG_AW {1} \ - CONFIG.REG_B {1} \ - CONFIG.REG_R {1} \ - CONFIG.REG_W {1} \ - ] $s03_rs_1 + set_property -dict [list \ + CONFIG.REG_AR {7} \ + CONFIG.REG_AW {7} \ + CONFIG.REG_B {7} \ + CONFIG.REG_R {1} \ + CONFIG.REG_W {1} \ + ] $s03_rs_1 + # Create instance: s03_width_conv, and set properties set s03_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s03_width_conv ] - set_property -dict [ list \ - CONFIG.ACLK_ASYNC {1} \ - CONFIG.FIFO_MODE {2} \ - CONFIG.MI_DATA_WIDTH {256} \ - CONFIG.SI_DATA_WIDTH {64} \ - CONFIG.SYNCHRONIZATION_STAGES {2} \ - ] $s03_width_conv + set_property -dict [list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.MI_DATA_WIDTH {256} \ + CONFIG.SI_DATA_WIDTH {64} \ + CONFIG.SYNCHRONIZATION_STAGES {2} \ + ] $s03_width_conv + # Create instance: xbar, and set properties set xbar [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 xbar ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {256} \ - CONFIG.ID_WIDTH {2} \ - CONFIG.NUM_MI {1} \ - CONFIG.NUM_SI {4} \ - CONFIG.S01_BASE_ID {0x00000001} \ - CONFIG.S02_BASE_ID {0x00000002} \ - CONFIG.S03_BASE_ID {0x00000003} \ - CONFIG.S04_BASE_ID {0x00000004} \ - CONFIG.S05_BASE_ID {0x00000005} \ - CONFIG.S06_BASE_ID {0x00000006} \ - CONFIG.S07_BASE_ID {0x00000007} \ - CONFIG.S08_BASE_ID {0x00000008} \ - CONFIG.S09_BASE_ID {0x00000009} \ - CONFIG.S10_BASE_ID {0x0000000a} \ - CONFIG.S11_BASE_ID {0x0000000b} \ - CONFIG.S12_BASE_ID {0x0000000c} \ - CONFIG.S13_BASE_ID {0x0000000d} \ - CONFIG.S14_BASE_ID {0x0000000e} \ - CONFIG.S15_BASE_ID {0x0000000f} \ - CONFIG.STRATEGY {2} \ - ] $xbar + set_property -dict [list \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.ID_WIDTH {2} \ + CONFIG.M00_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_READ_ISSUING {8} \ + CONFIG.M00_WRITE_ISSUING {8} \ + CONFIG.M01_A00_ADDR_WIDTH {0} \ + CONFIG.M01_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_READ_ISSUING {8} \ + CONFIG.M01_WRITE_ISSUING {8} \ + CONFIG.M02_A00_ADDR_WIDTH {0} \ + CONFIG.M02_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_READ_ISSUING {8} \ + CONFIG.M02_WRITE_ISSUING {8} \ + CONFIG.M03_A00_ADDR_WIDTH {0} \ + CONFIG.M03_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_READ_ISSUING {8} \ + CONFIG.M03_WRITE_ISSUING {8} \ + CONFIG.M04_A00_ADDR_WIDTH {0} \ + CONFIG.M04_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_READ_ISSUING {8} \ + CONFIG.M04_WRITE_ISSUING {8} \ + CONFIG.M05_A00_ADDR_WIDTH {0} \ + CONFIG.M05_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_READ_ISSUING {8} \ + CONFIG.M05_WRITE_ISSUING {8} \ + CONFIG.M06_A00_ADDR_WIDTH {0} \ + CONFIG.M06_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_READ_ISSUING {8} \ + CONFIG.M06_WRITE_ISSUING {8} \ + CONFIG.M07_A00_ADDR_WIDTH {0} \ + CONFIG.M07_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_READ_ISSUING {8} \ + CONFIG.M07_WRITE_ISSUING {8} \ + CONFIG.M08_A00_ADDR_WIDTH {0} \ + CONFIG.M08_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_READ_ISSUING {8} \ + CONFIG.M08_WRITE_ISSUING {8} \ + CONFIG.M09_A00_ADDR_WIDTH {0} \ + CONFIG.M09_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_READ_ISSUING {8} \ + CONFIG.M09_WRITE_ISSUING {8} \ + CONFIG.M10_A00_ADDR_WIDTH {0} \ + CONFIG.M10_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_READ_ISSUING {8} \ + CONFIG.M10_WRITE_ISSUING {8} \ + CONFIG.M11_A00_ADDR_WIDTH {0} \ + CONFIG.M11_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_READ_ISSUING {8} \ + CONFIG.M11_WRITE_ISSUING {8} \ + CONFIG.M12_A00_ADDR_WIDTH {0} \ + CONFIG.M12_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_READ_ISSUING {8} \ + CONFIG.M12_WRITE_ISSUING {8} \ + CONFIG.M13_A00_ADDR_WIDTH {0} \ + CONFIG.M13_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_READ_ISSUING {8} \ + CONFIG.M13_WRITE_ISSUING {8} \ + CONFIG.M14_A00_ADDR_WIDTH {0} \ + CONFIG.M14_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_READ_ISSUING {8} \ + CONFIG.M14_WRITE_ISSUING {8} \ + CONFIG.M15_A00_ADDR_WIDTH {0} \ + CONFIG.M15_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_READ_ISSUING {8} \ + CONFIG.M15_WRITE_ISSUING {8} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {4} \ + CONFIG.S00_READ_ACCEPTANCE {4} \ + CONFIG.S00_WRITE_ACCEPTANCE {4} \ + CONFIG.S01_BASE_ID {0x00000001} \ + CONFIG.S01_READ_ACCEPTANCE {4} \ + CONFIG.S01_WRITE_ACCEPTANCE {4} \ + CONFIG.S02_BASE_ID {0x00000002} \ + CONFIG.S02_READ_ACCEPTANCE {4} \ + CONFIG.S02_WRITE_ACCEPTANCE {4} \ + CONFIG.S03_BASE_ID {0x00000003} \ + CONFIG.S03_READ_ACCEPTANCE {4} \ + CONFIG.S03_WRITE_ACCEPTANCE {4} \ + CONFIG.S04_BASE_ID {0x00000004} \ + CONFIG.S04_READ_ACCEPTANCE {4} \ + CONFIG.S04_WRITE_ACCEPTANCE {4} \ + CONFIG.S05_BASE_ID {0x00000005} \ + CONFIG.S05_READ_ACCEPTANCE {4} \ + CONFIG.S05_WRITE_ACCEPTANCE {4} \ + CONFIG.S06_BASE_ID {0x00000006} \ + CONFIG.S06_READ_ACCEPTANCE {4} \ + CONFIG.S06_WRITE_ACCEPTANCE {4} \ + CONFIG.S07_BASE_ID {0x00000007} \ + CONFIG.S07_READ_ACCEPTANCE {4} \ + CONFIG.S07_WRITE_ACCEPTANCE {4} \ + CONFIG.S08_BASE_ID {0x00000008} \ + CONFIG.S08_READ_ACCEPTANCE {4} \ + CONFIG.S08_WRITE_ACCEPTANCE {4} \ + CONFIG.S09_BASE_ID {0x00000009} \ + CONFIG.S09_READ_ACCEPTANCE {4} \ + CONFIG.S09_WRITE_ACCEPTANCE {4} \ + CONFIG.S10_BASE_ID {0x0000000a} \ + CONFIG.S10_READ_ACCEPTANCE {4} \ + CONFIG.S10_WRITE_ACCEPTANCE {4} \ + CONFIG.S11_BASE_ID {0x0000000b} \ + CONFIG.S11_READ_ACCEPTANCE {4} \ + CONFIG.S11_WRITE_ACCEPTANCE {4} \ + CONFIG.S12_BASE_ID {0x0000000c} \ + CONFIG.S12_READ_ACCEPTANCE {4} \ + CONFIG.S12_WRITE_ACCEPTANCE {4} \ + CONFIG.S13_BASE_ID {0x0000000d} \ + CONFIG.S13_READ_ACCEPTANCE {4} \ + CONFIG.S13_WRITE_ACCEPTANCE {4} \ + CONFIG.S14_BASE_ID {0x0000000e} \ + CONFIG.S14_READ_ACCEPTANCE {4} \ + CONFIG.S14_WRITE_ACCEPTANCE {4} \ + CONFIG.S15_BASE_ID {0x0000000f} \ + CONFIG.S15_READ_ACCEPTANCE {4} \ + CONFIG.S15_WRITE_ACCEPTANCE {4} \ + CONFIG.STRATEGY {2} \ + ] $xbar + # Create interface connections connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports S00_AXI] [get_bd_intf_pins s00_rs_0/S_AXI] @@ -533,16 +888,52 @@ proc create_root_design { parentCell } { connect_bd_intf_net -intf_net xbar_M00_AXI [get_bd_intf_pins m00_rs/S_AXI] [get_bd_intf_pins xbar/M00_AXI] # Create port connections - connect_bd_net -net M00_AXI_ACLK_1 [get_bd_ports M00_AXI_ACLK] [get_bd_pins m00_rs/aclk] [get_bd_pins s00_rs_1/aclk] [get_bd_pins s00_width_conv/m_axi_aclk] [get_bd_pins s01_rs_1/aclk] [get_bd_pins s01_width_conv/m_axi_aclk] [get_bd_pins s02_rs_1/aclk] [get_bd_pins s02_width_conv/m_axi_aclk] [get_bd_pins s03_rs_1/aclk] [get_bd_pins s03_width_conv/m_axi_aclk] [get_bd_pins xbar/aclk] - connect_bd_net -net M00_AXI_ARESETN_1 [get_bd_ports M00_AXI_ARESETN] [get_bd_pins m00_rs/aresetn] [get_bd_pins s00_rs_1/aresetn] [get_bd_pins s00_width_conv/m_axi_aresetn] [get_bd_pins s01_rs_1/aresetn] [get_bd_pins s01_width_conv/m_axi_aresetn] [get_bd_pins s02_rs_1/aresetn] [get_bd_pins s02_width_conv/m_axi_aresetn] [get_bd_pins s03_rs_1/aresetn] [get_bd_pins s03_width_conv/m_axi_aresetn] [get_bd_pins xbar/aresetn] - connect_bd_net -net S00_AXI_ACLK_1 [get_bd_ports S00_AXI_ACLK] [get_bd_pins s00_rs_0/aclk] [get_bd_pins s00_width_conv/s_axi_aclk] - connect_bd_net -net S00_AXI_ARESETN_1 [get_bd_ports S00_AXI_ARESETN] [get_bd_pins s00_rs_0/aresetn] [get_bd_pins s00_width_conv/s_axi_aresetn] - connect_bd_net -net S01_AXI_ACLK_1 [get_bd_ports S01_AXI_ACLK] [get_bd_pins s01_rs_0/aclk] [get_bd_pins s01_width_conv/s_axi_aclk] - connect_bd_net -net S01_AXI_ARESETN_1 [get_bd_ports S01_AXI_ARESETN] [get_bd_pins s01_rs_0/aresetn] [get_bd_pins s01_width_conv/s_axi_aresetn] - connect_bd_net -net S02_AXI_ACLK_1 [get_bd_ports S02_AXI_ACLK] [get_bd_pins s02_rs_0/aclk] [get_bd_pins s02_width_conv/s_axi_aclk] - connect_bd_net -net S02_AXI_ARESETN_1 [get_bd_ports S02_AXI_ARESETN] [get_bd_pins s02_rs_0/aresetn] [get_bd_pins s02_width_conv/s_axi_aresetn] - connect_bd_net -net S03_AXI_ACLK_1 [get_bd_ports S03_AXI_ACLK] [get_bd_pins s03_rs_0/aclk] [get_bd_pins s03_width_conv/s_axi_aclk] - connect_bd_net -net S03_AXI_ARESETN_1 [get_bd_ports S03_AXI_ARESETN] [get_bd_pins s03_rs_0/aresetn] [get_bd_pins s03_width_conv/s_axi_aresetn] + connect_bd_net -net M00_AXI_ACLK_1 [get_bd_ports M00_AXI_ACLK] \ + [get_bd_pins m00_rs/aclk] \ + [get_bd_pins s00_rs_1/aclk] \ + [get_bd_pins s00_width_conv/m_axi_aclk] \ + [get_bd_pins s01_rs_1/aclk] \ + [get_bd_pins s01_width_conv/m_axi_aclk] \ + [get_bd_pins s02_rs_1/aclk] \ + [get_bd_pins s02_width_conv/m_axi_aclk] \ + [get_bd_pins s03_rs_1/aclk] \ + [get_bd_pins s03_width_conv/m_axi_aclk] \ + [get_bd_pins xbar/aclk] + connect_bd_net -net M00_AXI_ARESETN_1 [get_bd_ports M00_AXI_ARESETN] \ + [get_bd_pins m00_rs/aresetn] \ + [get_bd_pins s00_rs_1/aresetn] \ + [get_bd_pins s00_width_conv/m_axi_aresetn] \ + [get_bd_pins s01_rs_1/aresetn] \ + [get_bd_pins s01_width_conv/m_axi_aresetn] \ + [get_bd_pins s02_rs_1/aresetn] \ + [get_bd_pins s02_width_conv/m_axi_aresetn] \ + [get_bd_pins s03_rs_1/aresetn] \ + [get_bd_pins s03_width_conv/m_axi_aresetn] \ + [get_bd_pins xbar/aresetn] + connect_bd_net -net S00_AXI_ACLK_1 [get_bd_ports S00_AXI_ACLK] \ + [get_bd_pins s00_rs_0/aclk] \ + [get_bd_pins s00_width_conv/s_axi_aclk] + connect_bd_net -net S00_AXI_ARESETN_1 [get_bd_ports S00_AXI_ARESETN] \ + [get_bd_pins s00_rs_0/aresetn] \ + [get_bd_pins s00_width_conv/s_axi_aresetn] + connect_bd_net -net S01_AXI_ACLK_1 [get_bd_ports S01_AXI_ACLK] \ + [get_bd_pins s01_rs_0/aclk] \ + [get_bd_pins s01_width_conv/s_axi_aclk] + connect_bd_net -net S01_AXI_ARESETN_1 [get_bd_ports S01_AXI_ARESETN] \ + [get_bd_pins s01_rs_0/aresetn] \ + [get_bd_pins s01_width_conv/s_axi_aresetn] + connect_bd_net -net S02_AXI_ACLK_1 [get_bd_ports S02_AXI_ACLK] \ + [get_bd_pins s02_rs_0/aclk] \ + [get_bd_pins s02_width_conv/s_axi_aclk] + connect_bd_net -net S02_AXI_ARESETN_1 [get_bd_ports S02_AXI_ARESETN] \ + [get_bd_pins s02_rs_0/aresetn] \ + [get_bd_pins s02_width_conv/s_axi_aresetn] + connect_bd_net -net S03_AXI_ACLK_1 [get_bd_ports S03_AXI_ACLK] \ + [get_bd_pins s03_rs_0/aclk] \ + [get_bd_pins s03_width_conv/s_axi_aclk] + connect_bd_net -net S03_AXI_ARESETN_1 [get_bd_ports S03_AXI_ARESETN] \ + [get_bd_pins s03_rs_0/aresetn] \ + [get_bd_pins s03_width_conv/s_axi_aresetn] # Create address segments assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces S00_AXI] [get_bd_addr_segs M00_AXI/Reg] -force diff --git a/fpga/usrp3/top/b300/ip/bus_clk_gen/bus_clk_gen.xci b/fpga/usrp3/top/b300/ip/bus_clk_gen/bus_clk_gen.xci index 849babf7b..fa3fe91d2 100644 --- a/fpga/usrp3/top/b300/ip/bus_clk_gen/bus_clk_gen.xci +++ b/fpga/usrp3/top/b300/ip/bus_clk_gen/bus_clk_gen.xci @@ -1,761 +1,709 @@ - - - xilinx.com - xci - unknown - 1.0 - - - bus_clk_gen - - - false - 100000000 - false - 100000000 - false - 100000000 - false - 100000000 - - - - 100000000 - 0 - 0 - 0.0 - - - - 100000000 - 0 - 0 - 0.0 - - - - 100000000 - 0 - 0 - 0.0 - - - - 100000000 - 0 - 0 - 0.0 - 1 - LEVEL_HIGH - - - - 100000000 - 0 - 0 - 0.0 - 0 - 0 - - 100000000 - 0 - 0 - 0.0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.0 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - MMCM - cddcdone - cddcreq - 0000 - 0000 - clkfb_in_n - clkfb_in - clkfb_in_p - SINGLE - clkfb_out_n - clkfb_out - clkfb_out_p - clkfb_stopped - 80.0 - 100.0 - 0000 - 0000 - 150.00000 - 0000 - 0000 - 40.00000 - BUFG - 50.0 - false - 150.00000 - 0.000 - 50.000 - 150 - 0.000 - 1 - 0000 - 0000 - 200.00000 - BUFG - 50.0 - false - 40.00000 - 0.000 - 50.000 - 40 - 0.000 - 1 - 1 - 0000 - 0000 - 100.000 - BUFG - 50.0 - false - 200.00000 - 0.000 - 50.000 - 200 - 0.000 - 1 - 1 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - VCO - clk_in_sel - clk_out1 - clk_out2 - clk_out3 - clk_out4 - clk_out5 - clk_out6 - clk_out7 - CLK_VALID - NA - daddr - dclk - den - din - 0000 - 1 - 3.75 - 0.75 - 0.25 - 0.25 - 0.25 - 0.25 - dout - drdy - dwe - 80.000 - 1.000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - FDBK_AUTO - 0000 - 0000 - 0 - Input Clock Freq (MHz) Input Jitter (UI) - __primary_____________125____________0.010 - no_secondary_input_clock - input_clk_stopped - 0 - Units_MHz - No_Jitter - locked - 0000 - 0000 - 0000 - false - false - false - false - false - false - false - false - OPTIMIZED - 24.000 - 0.000 - FALSE - 8.0 - 10.0 - 4.000 - 0.500 - 0.000 - FALSE - 15 - 0.500 - 0.000 - FALSE - 3 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - FALSE - ZHOLD - 5 - None - 0.010 - 0.010 - FALSE - 64.000 - 2.000 - 3 - 0 - Output Output Phase Duty Cycle Pk-to-Pk Phase - Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - clk_out1__150.00000______0.000______50.0______291.314____335.459 - clk_out2__40.00000______0.000______50.0______376.602____335.459 - clk_out3__200.00000______0.000______50.0______275.885____335.459 - no_CLK_OUT4_output - no_CLK_OUT5_output - no_CLK_OUT6_output - no_CLK_OUT7_output - 0 - 0 - 128.000 - 1.000 - WAVEFORM - UNKNOWN - false - false - false - false - false - OPTIMIZED - 1 - 0.000 - 1.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - CLKFBOUT - SYSTEM_SYNCHRONOUS - 1 - No notes - 0.010 - power_down - 0000 - 1 - clk_in1 - MMCM - AUTO - 125 - 0.010 - 10.000 - Global_buffer - psclk - psdone - psen - psincdec - 100.0 - 0 - reset - 100.000 - 0.010 - 10.000 - clk_in2 - Single_ended_clock_capable_pin - CENTER_HIGH - 4000 - 0.004 - STATUS - 11 - 32 - 100.0 - 100.0 - 100.0 - 100.0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 1 - 0 - 1 - 0 - 0 - 0 - 1200.000 - 600.000 - bus_clk_gen - MMCM - false - empty - cddcdone - cddcreq - clkfb_in_n - clkfb_in - clkfb_in_p - SINGLE - clkfb_out_n - clkfb_out - clkfb_out_p - clkfb_stopped - 80.0 - 0.010 - 100.0 - 0.010 - BUFG - 291.314 - false - 335.459 - 50.000 - 150 - 0.000 - 1 - true - BUFG - 376.602 - false - 335.459 - 50.000 - 40 - 0.000 - 1 - true - BUFG - 275.885 - false - 335.459 - 50.000 - 200 - 0.000 - 1 - true - BUFG - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - BUFG - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - BUFG - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - BUFG - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - 600.000 - Custom - Custom - clk_in_sel - clk_out1 - false - clk_out2 - false - clk_out3 - false - clk_out4 - false - clk_out5 - false - clk_out6 - false - clk_out7 - false - CLK_VALID - auto - bus_clk_gen - daddr - dclk - den - Custom - Custom - din - dout - drdy - dwe - false - false - false - false - false - false - false - false - false - FDBK_AUTO - input_clk_stopped - frequency - Enable_AXI - Units_MHz - Units_UI - UI - No_Jitter - locked - OPTIMIZED - 24.000 - 0.000 - false - 8.0 - 10.0 - 4.000 - 0.500 - 0.000 - false - 15 - 0.500 - 0.000 - false - 3 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - false - ZHOLD - 5 - None - 0.010 - 0.010 - false - 3 - false - false - false - WAVEFORM - false - UNKNOWN - OPTIMIZED - 4 - 0.000 - 4.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - CLKFBOUT - SYSTEM_SYNCHRONOUS - 1 - None - 0.010 - power_down - 1 - clk_in1 - MMCM - mmcm_adv - 125 - 0.010 - 10.000 - Global_buffer - psclk - psdone - psen - psincdec - 100.0 - REL_PRIMARY - Custom - reset - ACTIVE_HIGH - 100.000 - 0.010 - 10.000 - clk_in2 - Single_ended_clock_capable_pin - CENTER_HIGH - 250 - 0.004 - STATUS - empty - 100.0 - 100.0 - 100.0 - 100.0 - false - false - false - false - false - false - false - true - false - false - true - false - false - false - true - false - true - false - false - false - kintex7 - - - xc7k325t - fbg676 - VERILOG - - MIXED - -1 - - - TRUE - TRUE - IP_Flow - 8 - TRUE - . - - . - 2021.1_AR76780 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "bus_clk_gen", + "component_reference": "xilinx.com:ip:clk_wiz:6.0", + "ip_revision": "17", + "gen_directory": ".", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "bus_clk_gen", "resolve_type": "user", "usage": "all" } ], + "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIMITIVE": [ { "value": "MMCM", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ], + "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ], + "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ], + "PRIM_IN_FREQ": [ { "value": "125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ], + "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ], + "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ], + "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ], + "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ], + "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], + "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ], + "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN1_JITTER_PS": [ { "value": "80.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "NUM_OUT_CLKS": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ], + "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ], + "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ], + "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ], + "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ], + "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ], + "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ], + "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ], + "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ], + "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ], + "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ], + "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "150", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIM_SOURCE": [ { "value": "Global_buffer", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT2_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT3_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT4_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT5_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT6_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT7_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ], + "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ], + "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ], + "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ], + "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ], + "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ], + "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ], + "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ], + "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ], + "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ], + "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ], + "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ], + "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "MMCM_DIVCLK_DIVIDE": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "MMCM_CLKFBOUT_MULT_F": [ { "value": "24.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKIN1_PERIOD": [ { "value": "8.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_COMPENSATION": [ { "value": "ZHOLD", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "4.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT2_DIVIDE": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ], + "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKIN_PERIOD": [ { "value": "4.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ], + "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ], + "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], 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"false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ], + "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], + "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ], + "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN1_JITTER_PS": [ { "value": "80.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "NUM_OUT_CLKS": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ], + "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ], + "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ], + "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ], + "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ], + "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ], + "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ], + "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ], + "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ], + "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ], + "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ], + "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "125.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_PHASE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "40.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "166.66667", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_PHASE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIM_SOURCE": [ { "value": "No_buffer", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT2_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT3_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT4_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT5_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT6_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT7_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ], + "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ], + "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ], + "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ], + "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ], + "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ], + "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ], + "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ], + "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ], + "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ], + "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ], + "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ], + "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "MMCM_CLKFBOUT_MULT_F": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKIN1_PERIOD": [ { "value": "8.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_COMPENSATION": [ { "value": "ZHOLD", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "25", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT2_DIVIDE": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT3_DIVIDE": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ], + "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKIN_PERIOD": [ { "value": "8.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ], + "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + 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100644 --- a/fpga/usrp3/top/b300/ip/ref_clk_pll/ref_clk_pll.xci +++ b/fpga/usrp3/top/b300/ip/ref_clk_pll/ref_clk_pll.xci @@ -1,744 +1,671 @@ - - - xilinx.com - xci - unknown - 1.0 - - - ref_clk_pll - - - false - 100000000 - false - 100000000 - false - 100000000 - false - 100000000 - - - - 100000000 - 0 - 0 - 0.0 - - - - 100000000 - 0 - 0 - 0.0 - 1 - LEVEL_HIGH - - - - 100000000 - 0 - 0 - 0.0 - 0 - 0 - - 100000000 - 0 - 0 - 0.0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.0 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - MMCM - cddcdone - cddcreq - 0000 - 0000 - clkfb_in_n - clkfb_in - clkfb_in_p - SINGLE - clkfb_out_n - clkfb_out - clkfb_out_p - clkfb_stopped - 80.0 - 100.0 - 0000 - 0000 - 125.00000 - 0000 - 0000 - 100.000 - BUFG - 50.0 - false - 125.00000 - 0.000 - 50.000 - 125.000 - 0.000 - 1 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 40 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 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+ "ip_revision": "17", + "gen_directory": ".", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "ref_clk_pll", "resolve_type": "user", "usage": "all" } ], + "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIMITIVE": [ { "value": "PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ], + "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ], + "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "JITTER_SEL": [ { "value": "No_Jitter", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PRIM_IN_FREQ": [ { "value": "125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ], + "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ], + "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ], + "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ], + "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ], + "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], + "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ], + "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN1_JITTER_PS": [ { "value": "80.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_USED": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_USED": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "NUM_OUT_CLKS": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ], + "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ], + "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ], + "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ], + "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ], + "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ], + "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ], + "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ], + "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ], + "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ], + "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ], + "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "125.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIM_SOURCE": [ { "value": "No_buffer", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT2_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT3_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT4_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT5_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT6_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT7_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ], + "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ], + "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ], + "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ], + "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ], + "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ], + "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ], + "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ], + "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ], + "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ], + "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ], + "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ], + "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "MMCM_CLKFBOUT_MULT_F": [ { "value": "7", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKIN1_PERIOD": [ { "value": "8.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_COMPENSATION": [ { "value": "ZHOLD", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "7", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OVERRIDE_PLL": [ { "value": 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], + "C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ], + "C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], 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"is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "reset" } ] + } + }, + "clock_CLK_IN1": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], + "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ] + }, + "port_maps": { + "CLK_IN1": [ { "physical_name": "clk_in1" } ] + } + }, + "clock_CLK_OUT1": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "master", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK_OUT1": [ { "physical_name": "clk_out1" } ] + } + } + } + } + }, + "checksum": "84bf69b1" +} \ No newline at end of file diff --git a/fpga/usrp3/top/b300/setupenv.sh b/fpga/usrp3/top/b300/setupenv.sh index f0cb55c48..e7740e1ec 100644 --- a/fpga/usrp3/top/b300/setupenv.sh +++ b/fpga/usrp3/top/b300/setupenv.sh @@ -1,7 +1,7 @@ #!/bin/bash -VIVADO_VER=2021.1 -VIVADO_VER_FULL=2021.1_AR76780 +VIVADO_VER=2025.2 +VIVADO_VER_FULL=2025.2 DISPLAY_NAME="USRP-B310" REPO_BASE_PATH=$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)