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host: x4xx: update default wait time for NCO reset
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parent
7b7f518ad4
commit
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@ -24,6 +24,9 @@ class rfdc_control
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public:
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public:
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using sptr = std::shared_ptr<rfdc_control>;
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using sptr = std::shared_ptr<rfdc_control>;
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//! Default SYSREF wait time for an NCO reset, in SYSREF cycles
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static constexpr uint32_t DEFAULT_SYSREF_WAIT_CYCLES = 14;
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struct regmap
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struct regmap
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{
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{
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//! Address of the NCO reset register
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//! Address of the NCO reset register
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@ -27,8 +27,9 @@ void rfdc_control::reset_ncos(
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}
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}
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UHD_LOG_TRACE(_log_id, "Resetting " << ncos.size() << " NCOs...");
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UHD_LOG_TRACE(_log_id, "Resetting " << ncos.size() << " NCOs...");
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// Initialize the NCO reset delay to a default of 11 SYSREF cycles
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// Initialize the NCO reset delay to the default number of SYSREF cycles
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constexpr uint32_t reset_word = (11 & 0xFF) << regmap::SYSREF_WAIT_LSB
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constexpr uint32_t reset_word = (DEFAULT_SYSREF_WAIT_CYCLES & 0xFF)
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<< regmap::SYSREF_WAIT_LSB
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| 0x1 << regmap::WRITE_SYSREF_WAIT | 1;
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| 0x1 << regmap::WRITE_SYSREF_WAIT | 1;
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// Initiate NCO reset
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// Initiate NCO reset
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@ -778,7 +778,8 @@ BOOST_FIXTURE_TEST_CASE(zbx_phase_sync_test, x400_radio_fixture)
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// Set reset complete bit
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// Set reset complete bit
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regs[nco_sync_addr] = 1 << 1;
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regs[nco_sync_addr] = 1 << 1;
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constexpr uint32_t nco_sync_val =
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constexpr uint32_t nco_sync_val =
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(11 & 0xFF) << uhd::rfnoc::x400::rfdc_control::regmap::SYSREF_WAIT_LSB
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(uhd::rfnoc::x400::rfdc_control::DEFAULT_SYSREF_WAIT_CYCLES & 0xFF)
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<< uhd::rfnoc::x400::rfdc_control::regmap::SYSREF_WAIT_LSB
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| 1 << uhd::rfnoc::x400::rfdc_control::regmap::WRITE_SYSREF_WAIT
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| 1 << uhd::rfnoc::x400::rfdc_control::regmap::WRITE_SYSREF_WAIT
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| 1 << uhd::rfnoc::x400::rfdc_control::regmap::NCO_RESET_DONE_MSB
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| 1 << uhd::rfnoc::x400::rfdc_control::regmap::NCO_RESET_DONE_MSB
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| 1 << uhd::rfnoc::x400::rfdc_control::regmap::NCO_RESET_START_MSB;
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| 1 << uhd::rfnoc::x400::rfdc_control::regmap::NCO_RESET_START_MSB;
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