hero123457/uhd
1
0
Fork 0
mirror of https://github.com/EttusResearch/uhd.git synced 2026-10-25 17:36:10 +00:00
Code Issues Projects Releases Wiki Activity

fpga: ci: add b310 option to FPGA pipeline

Browse Source
This commit is contained in:
Max Köhler 2026-09-15 18:09:54 +02:00 committed by mkoop-ni
parent 3f46b68c6d
commit 3fe3610eb8
1 changed files with 6 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
fpga/.ci/fpga-pipeline.yml
View File

@ -29,6 +29,10 @@ parameters:
type: boolean
displayName: Build N3xx
default: false
- name: build_b310
type: boolean
displayName: Build B310
default: false
- name: build_e31x
type: boolean
displayName: Build E31x
@ -234,10 +238,11 @@ extends:
parameters:
add_tests: ${{
format(
'{0};{1};{2};{3};{4};{5};{6};{7};{8};{9};{10};',
'{0};{1};{2};{3};{4};{5};{6};{7};{8};{9};{10};{11};',
iif(parameters.run_testbenches,'fpga.usrp3.testbenches',''),
iif(parameters.build_x3x0,'fpga.usrp3.x3xx',''),
iif(parameters.build_n3xx,'fpga.usrp3.n3xx',''),
iif(parameters.build_b310,'fpga.usrp3.b310',''),
iif(parameters.build_e31x,'fpga.usrp3.e31x',''),
iif(parameters.build_e320,'fpga.usrp3.e320',''),
iif(parameters.build_x410,'fpga.usrp3.x410',''),