hero123457/uhd
1
0
Fork 0
mirror of https://github.com/EttusResearch/uhd.git synced 2026-10-25 17:36:10 +00:00
Code Issues Projects Releases Wiki Activity

fpga: b310: Fix synthesis-only builds

Browse Source
This commit is contained in:
Wade Fife 2026-08-19 22:44:16 -05:00 committed by mkoop-ni
parent 0e3b241021
commit 000cd8e3cb
3 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
fpga/usrp3/top/b300/Makefile
View File

@ -38,8 +38,6 @@ BASE_DEFS= $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
ifndef TARGET ifndef TARGET
ifeq ($(CHECK), 1) ifeq ($(CHECK), 1)
TARGET = rtl TARGET = rtl
else ifeq ($(SYNTH), 1)
TARGET = synth
else ifeq ($(IP_ONLY), 1) else ifeq ($(IP_ONLY), 1)
TARGET = viv_ip TARGET = viv_ip
else else
@ -53,7 +51,11 @@ vivado_build = make -f Makefile.b310.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) P
vivado_ip = make -f Makefile.b310.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" vivado_ip = make -f Makefile.b310.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
# post_build($1=Device, $2=Option) # post_build($1=Device, $2=Option)
ifeq ($(TARGET),bin) # Only export build artifacts for a full build (TARGET=bin) and not synthesis
# only (SYNTH=1). Normalize SYNTH so that only the value 1 is treated as
# synthesis only; 0 or unset are equivalent.
SYNTH_ONLY := $(filter 1,$(SYNTH))
ifeq ($(TARGET)$(SYNTH_ONLY),bin)
post_build = @\ post_build = @\
mkdir -p $(BUILD_OUTPUT_DIR); \ mkdir -p $(BUILD_OUTPUT_DIR); \
echo "Exporting bitstream files..."; \ echo "Exporting bitstream files..."; \

5
fpga/usrp3/top/b300/Makefile.b310.inc
View File

@ -104,13 +104,10 @@ bin: .prereqs
@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)" @echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"
$(call BUILD_VIVADO_DESIGN,$(abspath ./build_b310.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID)) $(call BUILD_VIVADO_DESIGN,$(abspath ./build_b310.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
synth: .prereqs
$(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
rtl: .prereqs rtl: .prereqs
$(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) $(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
viv_ip: .prereqs $$(DESIGN_SRCS) ip viv_ip: .prereqs $$(DESIGN_SRCS) ip
@echo "IP build for $(NAME) DONE . . ." @echo "IP build for $(NAME) DONE . . ."
.PHONY: bin synth rtl viv_ip .PHONY: bin rtl viv_ip

1
fpga/usrp3/top/b300/build_b310.tcl
View File

@ -13,6 +13,7 @@ vivado_utils::initialize_project
# STEP#2: Run synthesis # STEP#2: Run synthesis
vivado_utils::synthesize_design vivado_utils::synthesize_design
vivado_utils::generate_post_synth_reports vivado_utils::generate_post_synth_reports
vivado_utils::exit_if_synth_only
# STEP#3: Run implementation strategy # STEP#3: Run implementation strategy
set b310_strategy [dict create] set b310_strategy [dict create]