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https://github.com/EttusResearch/uhd.git
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e6470cf8ce
Extend GPIO SPI transactions up to 64 bits and update the X4xx FPGA register map and RTL to support the new access width. Migrate the GPIO SPI register definitions to SystemVerilog. Add testbench for X4xx GPIO SPI module covering both exisiting 32bit functionality and added 64bit functionality. Separate TB Makefiles for X4xx and X410 implementation variant. Bump the FPGA compatibility number so host and MPM software can reject images that do not provide the required GPIO SPI register interface.
687 lines
25 KiB
Systemverilog
687 lines
25 KiB
Systemverilog
//
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// Copyright 2026 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: x4xx_gpio_spi
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//
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// Description:
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//
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// This block enables control of a SPI master engine via CtrlPort
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// transactions.
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// It also enables customization on how signals from the SPI buses
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// connected to the master are mapped to the GPIO Ports.
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// This block supports configuring communication to up to 4 SPI slaves.
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//
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// Parameters:
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//
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// NUM_SLAVES : Number of SPI slaves to be supported. Values from 1 to 4
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// are supported. SPI transfers can only target one slave
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// at a time.
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// BASE_ADDRESS : Start address for this register block.
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// SIZE_ADDRESS : Size of the CtrlPort window to consider in this block.
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//
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`default_nettype none
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module x4xx_gpio_spi #(
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parameter NUM_SLAVES = 4,
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parameter [19:0] BASE_ADDRESS = 0,
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parameter [19:0] SIZE_ADDRESS = 19'h2C
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) (
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input wire ctrlport_clk,
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input wire ctrlport_clk_2x,
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input wire ctrlport_rst,
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// Request
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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// Response
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output reg s_ctrlport_resp_ack = 1'b0,
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output reg [ 1:0] s_ctrlport_resp_status = 2'b0,
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output reg [31:0] s_ctrlport_resp_data = 32'b0,
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// GPIO control/status
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output wire [31:0] gpio_out,
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output wire [31:0] gpio_ddr,
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input wire [31:0] gpio_in
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);
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`include "../../lib/rfnoc/core/ctrlport.vh"
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import XmlSvPkgDIG_IFC_REGMAP::*;
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// Registers / wires for SPI core communication
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reg [31:0] set_data = 0;
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reg [ 7:0] set_addr = 0;
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reg set_stb = 1'b0;
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wire [63:0] readback;
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wire readback_stb;
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wire readback_stb_extended;
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wire sclk;
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wire mosi;
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wire miso;
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// This array is set to the maximum supported SPI slaves instead of
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// the provided NUM_SLAVES to facilitate concurrent re-mapping.
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// See section(GPIO Mapping) of this file.
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wire [3:0] ss;
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// Auxiliary signals to compute which GPIO lines are outputs
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reg [31:0] gpio_is_mosi = 32'b0;
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reg [31:0] gpio_is_sclk = 32'b0;
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reg [31:0] gpio_is_cs = 32'b0;
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// SPI-to-GPIO mapping signals.
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// These arrays are set to the maximum supported SPI slaves instead of
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// the provided NUM_SLAVES to facilitate concurrent re-mapping.
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// See section(GPIO Mapping) of this file.
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reg [kSLAVE_CLKSize-1:0] sclk_mapping [3:0];
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reg [kSLAVE_MOSISize-1:0] mosi_mapping [3:0];
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reg [kSLAVE_MISOSize-1:0] miso_mapping [3:0];
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reg [ kSLAVE_CSSize-1:0] ss_mapping [3:0];
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//---------------------------------------------------------------------------
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// Address calculation
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//---------------------------------------------------------------------------
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wire address_in_range =
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(s_ctrlport_req_addr >= BASE_ADDRESS) &&
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(s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);
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// Check that address is targeting slave configuration.
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wire address_is_slave =
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(s_ctrlport_req_addr >= BASE_ADDRESS + kSPI_SLAVE_CONFIG(0)) &&
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(s_ctrlport_req_addr <= BASE_ADDRESS + kSPI_SLAVE_CONFIG(3));
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// Decode the slave being addressed.
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wire [1:0]slave_address = s_ctrlport_req_addr[3:2];
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//---------------------------------------------------------------------------
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// Slave configuration signals
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//---------------------------------------------------------------------------
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// These settings are registered individually for each slave
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reg [ NUM_SLAVES-1:0] data_in_edge = {NUM_SLAVES{1'b0}};
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reg [ NUM_SLAVES-1:0] data_out_edge = {NUM_SLAVES{1'b0}};
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reg [kSPI_LENGTHSize-1:0] slave_spi_length [NUM_SLAVES-1:0];
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// One-hot encoding to indicate active slave
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reg [NUM_SLAVES-1:0] slave_select = {NUM_SLAVES{1'b0}};
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//---------------------------------------------------------------------------
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// FSM to handle transfers
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//---------------------------------------------------------------------------
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localparam IDLE = 3'd0;
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localparam SET_DIVIDER = 3'd1;
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localparam WRITE_SPI_LSB = 3'd2;
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localparam WRITE_SPI = 3'd3;
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localparam CONFIG_TRANSFER = 3'd4;
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localparam WAIT_SPI = 3'd5;
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// Addresses in simple_spi_core_64bit.v
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localparam DIVIDER_ADDRESS = 8'd0;
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localparam CTRL_ADDRESS = 8'd1;
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localparam DATA_ADDRESS = 8'd2;
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localparam DATA_LSB_ADDRESS = 8'd3;
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reg [ 2:0] state = IDLE;
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reg [ 31:0] data_cache;
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reg [kSPI_CLK_DIVSize-1:0] divider;
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reg [ 1:0] cs;
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reg spi_go = 1'b0;
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reg spi_ready = 1'b0;
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// Additional bits for optional 64 bit transaction
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reg [ 31:0] data_cache_lsb;
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integer slave_i;
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//---------------------------------------------------------------------------
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// CtrlPort Register endpoints
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//---------------------------------------------------------------------------
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always @ (posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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s_ctrlport_resp_ack <= 1'b0;
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spi_go <= 1'b0;
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spi_ready <= 1'b0;
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divider <= {kSPI_CLK_DIVSize{1'b0}};
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cs <= 2'b0;
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data_cache <= 32'h0;
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// Assigned to unassigned mapping (pin 31 is unused). This avoids
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// overwriting signals with those from uninitialized slaves.
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for ( slave_i = 0; slave_i < 4; slave_i = slave_i + 1 ) begin
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sclk_mapping[slave_i] <= 5'd31;
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mosi_mapping[slave_i] <= 5'd31;
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miso_mapping[slave_i] <= 5'd31;
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ss_mapping [slave_i] <= 5'd31;
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end
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for ( slave_i = 0; slave_i < NUM_SLAVES; slave_i = slave_i + 1) begin
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slave_spi_length[slave_i] <= {kSPI_LENGTHSize{1'b0}};
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end
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end else begin
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// Default assignments
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s_ctrlport_resp_ack <= 1'b0;
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spi_go <= 1'b0;
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// Requests appear
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if (s_ctrlport_req_wr) begin
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_data <= {32{1'bx}};
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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// Address spi configuration writes
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if(address_is_slave) begin
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automatic SPI_SETUP spi_setup = s_ctrlport_req_data;
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// GPIO mapping
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sclk_mapping [slave_address] <= spi_setup.SLAVE_CLK;
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mosi_mapping [slave_address] <= spi_setup.SLAVE_MOSI;
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miso_mapping [slave_address] <= spi_setup.SLAVE_MISO;
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ss_mapping [slave_address] <= spi_setup.SLAVE_CS;
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// Transfer Configuration
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slave_spi_length [slave_address] <= spi_setup.SPI_LENGTH;
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data_in_edge [slave_address] <= spi_setup.MISO_EDGE;
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data_out_edge [slave_address] <= spi_setup.MOSI_EDGE;
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end else begin
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case (s_ctrlport_req_addr)
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BASE_ADDRESS + kSPI_TRANSACTION_CONFIG: begin
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automatic SPI_TRANSACTION_CONFIG spi_transaction_config = s_ctrlport_req_data;
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divider <= spi_transaction_config.SPI_CLK_DIV;
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cs <= spi_transaction_config.SPI_SLAVE_SELECT;
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end
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BASE_ADDRESS + kSPI_TRANSACTION_LSB: begin
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data_cache_lsb <= s_ctrlport_req_data;
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end
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BASE_ADDRESS + kSPI_TRANSACTION_GO: begin
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spi_ready <= 1'b0;
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spi_go <= 1'b1;
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data_cache <= s_ctrlport_req_data;
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end
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// No register implementation for provided address
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default: begin
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// Acknowledge and provide error status if address is in range
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// No response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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end
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end else if(s_ctrlport_req_rd) begin
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// default assumption: valid request
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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s_ctrlport_resp_data <= {32{1'b0}};
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case (s_ctrlport_req_addr)
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BASE_ADDRESS + kSPI_TRANSACTION_CONFIG: begin
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automatic SPI_TRANSACTION_CONFIG spi_transaction_config = '0;
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spi_transaction_config.SPI_CLK_DIV = divider;
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s_ctrlport_resp_data <= spi_transaction_config;
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end
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BASE_ADDRESS + kSPI_STATUS: begin
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automatic SPI_STATUS spi_status = '0;
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spi_status.SPI_READY = spi_ready;
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spi_status.SPI_RESPONSE = readback[30:0];
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s_ctrlport_resp_data <= spi_status;
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end
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BASE_ADDRESS + kSPI_FULL_RESPONSE_MSB: begin
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automatic SPI_FULL_RESPONSE_MSB spi_full_response = '0;
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spi_full_response.SPI_FULL_RESPONSE_MSB_DATA = readback[62:31];
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s_ctrlport_resp_data <= spi_full_response;
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end
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BASE_ADDRESS + kCONTROLLER_INFO: begin
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automatic CONTROLLER_INFO controller_info = '0;
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controller_info.SLAVE_COUNT = NUM_SLAVES;
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s_ctrlport_resp_data <= controller_info;
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end
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// No register implementation for provided address
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default: begin
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// Acknowledge and provide error status if address is in range
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// No response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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end
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if (readback_stb_extended) begin
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spi_ready <= 1'b1;
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end
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end
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end
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//---------------------------------------------------------------------------
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// SPI Control FSM
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//---------------------------------------------------------------------------
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always @ (posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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state <= IDLE;
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set_stb <= 1'b0;
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end else begin
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// Default Assignments
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set_stb <= 1'b0;
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case (state)
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IDLE: begin
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if (spi_go) begin
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state <= CONFIG_TRANSFER;
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slave_select <= {NUM_SLAVES{1'b0}};
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slave_select[cs] <= 1'b1;
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end
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end
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// Set slave select
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CONFIG_TRANSFER: begin
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state <= SET_DIVIDER;
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set_stb <= 1'b1;
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set_addr <= CTRL_ADDRESS;
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set_data <= { data_out_edge[cs], // 1 bit
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data_in_edge[cs], // 1 bit
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slave_spi_length[cs][5:0], // 6 bits, ignore MSB, 0 is considered as 64
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{24-NUM_SLAVES{1'b0}}, // Padding for slaves
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slave_select // NUM_SLAVES bits
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};
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end
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// Write divider to SPI core
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SET_DIVIDER: begin
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if (slave_spi_length[cs] > 32) begin
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state <= WRITE_SPI_LSB;
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end else begin
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state <= WRITE_SPI;
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end
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set_stb <= 1'b1;
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set_addr <= DIVIDER_ADDRESS;
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set_data <= {16'b0, divider};
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end
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// Write data bits to SPI core (aligned to MSB)
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WRITE_SPI_LSB: begin
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state <= WRITE_SPI;
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set_stb <= 1'b1;
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set_addr <= DATA_LSB_ADDRESS;
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set_data <= data_cache_lsb;
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end
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// Write data bits to SPI core (aligned to MSB)
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WRITE_SPI: begin
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state <= WAIT_SPI;
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set_stb <= 1'b1;
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set_addr <= DATA_ADDRESS;
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set_data <= data_cache;
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end
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// Wait for transaction to complete and translate to ctrlport response
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WAIT_SPI: begin
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if (readback_stb_extended) begin
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state <= IDLE;
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end
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end
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default: begin
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state <= IDLE;
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end
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endcase
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// Update Auxiliary signals
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gpio_is_mosi <= 32'h0;
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gpio_is_sclk <= 32'h0;
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gpio_is_cs <= 32'h0;
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for ( slave_i = 0; slave_i < NUM_SLAVES; slave_i = slave_i + 1) begin
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gpio_is_mosi[mosi_mapping[slave_i]] <= 1'b1;
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gpio_is_sclk[sclk_mapping[slave_i]] <= 1'b1;
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gpio_is_cs [ ss_mapping[slave_i]] <= 1'b1;
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end
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end
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end
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//---------------------------------------------------------------------------
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// SPI master
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//---------------------------------------------------------------------------
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`ifndef X410
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simple_spi_core_64bit #(
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.BASE (0),
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.WIDTH (NUM_SLAVES),
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.CLK_IDLE (0),
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.SEN_IDLE ({NUM_SLAVES{1'b1}}),
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.MAX_BITS (64)
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) simple_spi_core_i (
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.clock (ctrlport_clk),
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.reset (ctrlport_rst),
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.set_stb (set_stb),
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.set_addr (set_addr),
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.set_data (set_data),
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.readback (readback),
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.readback_stb (readback_stb),
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.ready (),
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.sen (ss[NUM_SLAVES-1:0]),
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.sclk (sclk),
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.mosi (mosi),
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.miso (miso),
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.debug ()
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);
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assign readback_stb_extended = readback_stb;
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`else // X410
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// We only trigger one cycle of set_stb_2x per state change. This way the latency
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// is deterministic from the first change and aligned to the correct address,
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// without the need to pipeline the signal.
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// ┐ ┌─────┐ ┌─────┐ ┌─────┐ ┌─────┐ ┌─────┐
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//clk : └─────┘ └─────┘ └─────┘ └─────┘ └─────┘ └───
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// xxxxxx/ \/ \/ \xxxxxxxxxxxxxxxxxxxxxx
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//state : xxxxxx\ ctrl /\ div /\ data /xxxxxxxxxxxxxxxxxxxxxx
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// xxxxxxxxxxxxxxxxxx/ \/ \/ \xxxxxxxxxx
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//state_dlyd : xxxxxxxxxxxxxxxxxx\ ctrl /\ div /\ data /xxxxxxxxxx
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// ┐ ┌───────────────────────────────────┐
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//set_stb : └─────────────────┘ └─────────
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// xxxxxxxxxxxxxxxxxx/ \/ \/ \xxxxxxxxxx
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//set_addr : xxxxxxxxxxxxxxxxxx\ 0x1 /\ 0x0 /\ 0x2 /xxxxxxxxxx
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// ──┐ ┌──┐ ┌──┐ ┌──┐ ┌──┐ ┌──┐ ┌──┐ ┌──┐ ┌──┐ ┌──┐ ┌──┐
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//clk_2x : └──┘ └──┘ └──┘ └──┘ └──┘ └──┘ └──┘ └──┘ └──┘ └──┘ └
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// xxxxxxxxxxxxxxxxxxxxxxxx/ \/ \/ \xxxx
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//state_dlyd_2x: xxxxxxxxxxxxxxxxxxxxxxxx\ ctrl /\ div /\ data /xxxx
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// ┌─────┐ ┌─────┐ ┌─────┐
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//set_stb_2x : ────────────────────────┘ └─────┘ └─────┘ └─────────
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// ┌─────┐
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//trigger_spi : ──────────────────────────────────────────────────────┘ └───
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//
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reg set_stb_2x = 1'b0;
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reg [2:0] state_dlyd, state_dlyd_2x = IDLE;
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always @ (posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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state_dlyd <= IDLE;
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end else begin
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state_dlyd <= state;
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end
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end
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always @ (posedge ctrlport_clk_2x) begin
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if (ctrlport_rst) begin
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state_dlyd_2x <= IDLE;
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set_stb_2x <= 1'b0;
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end else begin
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state_dlyd_2x <= state_dlyd;
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set_stb_2x <= set_stb && (state_dlyd_2x != state_dlyd);
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end
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end
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simple_spi_core_64bit #(
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.BASE (0),
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.WIDTH (NUM_SLAVES),
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.CLK_IDLE (0),
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.SEN_IDLE ({NUM_SLAVES{1'b1}}),
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.MAX_BITS (64)
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) simple_spi_core_i (
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.clock (ctrlport_clk_2x),
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.reset (ctrlport_rst),
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.set_stb (set_stb_2x),
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.set_addr (set_addr),
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.set_data (set_data),
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.readback (readback),
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.readback_stb (readback_stb),
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.ready (),
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.sen (ss[NUM_SLAVES-1:0]),
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.sclk (sclk),
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.mosi (mosi),
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.miso (miso),
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.debug ()
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);
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// Delay and extend signal for use in 1x domain.
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reg readback_stb_dly = 1'b0;
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always @ (posedge ctrlport_clk_2x) begin
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readback_stb_dly <= readback_stb;
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end
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assign readback_stb_extended = readback_stb_dly | readback_stb;
|
|
|
|
`endif
|
|
|
|
//---------------------------------------------------------------------------
|
|
// GPIO Mapping
|
|
//---------------------------------------------------------------------------
|
|
|
|
wire [31:0] mosi_mux_out;
|
|
reg [31:0] mosi_mux_out_dlyd;
|
|
wire [31:0] ss_mux_out;
|
|
wire [31:0] gated_sclk;
|
|
reg [31:0] gated_sclk_dlyd;
|
|
reg [31:0] gpio_is_sclk_dlyd;
|
|
|
|
genvar i;
|
|
generate
|
|
|
|
for (i = 0; i < 32; i = i + 1) begin: dio_output_gen
|
|
|
|
// Indicate which GPIO lines are outputs
|
|
assign gpio_ddr[i] = gpio_is_mosi[i] | gpio_is_sclk[i] | gpio_is_cs[i];
|
|
|
|
// CS re-mapping
|
|
assign ss_mux_out[i] = ( i == ss_mapping[0] ) ? ss[0] :
|
|
( i == ss_mapping[1] ) ? ss[1] :
|
|
( i == ss_mapping[2] ) ? ss[2] :
|
|
( i == ss_mapping[3] ) ? ss[3] :
|
|
1'b0;
|
|
|
|
assign mosi_mux_out[i] = gpio_is_mosi[i] ? mosi : ss_mux_out[i];
|
|
assign gated_sclk[i] = gpio_is_sclk[i] ? sclk : 1'b0;
|
|
|
|
// register signals once remapping logic is resolved
|
|
`ifndef X410
|
|
always @ (posedge ctrlport_clk) begin
|
|
mosi_mux_out_dlyd[i] <= mosi_mux_out[i];
|
|
gpio_is_sclk_dlyd[i] <= gpio_is_sclk[i];
|
|
gated_sclk_dlyd[i] <= gated_sclk[i];
|
|
end
|
|
`else // X410
|
|
always @ (posedge ctrlport_clk_2x) begin
|
|
mosi_mux_out_dlyd[i] <= mosi_mux_out[i];
|
|
gpio_is_sclk_dlyd[i] <= gpio_is_sclk[i];
|
|
gated_sclk_dlyd[i] <= gated_sclk[i];
|
|
end
|
|
`endif
|
|
|
|
// Choose between SCLK and MOSI/SS mux.
|
|
glitch_free_mux glitch_free_gpio_out (
|
|
.select (gpio_is_sclk_dlyd[i]),
|
|
.signal0 (mosi_mux_out_dlyd[i]),
|
|
.signal1 (gated_sclk_dlyd[i]),
|
|
.muxed_signal (gpio_out[i])
|
|
);
|
|
|
|
end
|
|
endgenerate
|
|
|
|
assign miso = ( ~ss[0] ) ? gpio_in[miso_mapping[0]] :
|
|
( ~ss[1] ) ? gpio_in[miso_mapping[1]] :
|
|
( ~ss[2] ) ? gpio_in[miso_mapping[2]] :
|
|
( ~ss[3] ) ? gpio_in[miso_mapping[3]] :
|
|
1'b0;
|
|
|
|
|
|
endmodule
|
|
|
|
|
|
`default_nettype wire
|
|
|
|
//XmlParse xml_on
|
|
//<regmap name="DIG_IFC_REGMAP" readablestrobes="false">
|
|
// <group name="SPI_OVER_GPIO_REGS">
|
|
// <info>
|
|
// </info>
|
|
// <regtype name="SPI_SETUP" size="32">
|
|
// <info>
|
|
// Controls SPI Transaction
|
|
// </info>
|
|
// <bitfield name="SLAVE_CLK" range="0..4" initialvalue="0">
|
|
// <info>
|
|
// Indicates which GPIO line to use for the SCLK signal.</br>
|
|
// 0-11 : Port A GPIO</br>
|
|
// 16-27: Port B GPIO
|
|
// </info>
|
|
// </bitfield>
|
|
// <bitfield name="SLAVE_MOSI" range="5..9" initialvalue="0">
|
|
// <info>
|
|
// Indicates which GPIO line to use for the MOSI signal.</br>
|
|
// 0-11 : Port A GPIO</br>
|
|
// 16-27: Port B GPIO
|
|
// </info>
|
|
// </bitfield>
|
|
// <bitfield name="SLAVE_MISO" range="10..14" initialvalue="0">
|
|
// <info>
|
|
// Indicates which GPIO line to use for the MISO signal.</br>
|
|
// 0-11 : Port A GPIO</br>
|
|
// 16-27: Port B GPIO
|
|
// </info>
|
|
// </bitfield>
|
|
// <bitfield name="SLAVE_CS" range="15..19" initialvalue="0">
|
|
// <info>
|
|
// Indicates which GPIO line to use for the CS signal.</br>
|
|
// 0-11 : Port A GPIO</br>
|
|
// 16-27: Port B GPIO
|
|
// </info>
|
|
// </bitfield>
|
|
// <bitfield name="SPI_LENGTH" range="20..26" initialvalue="0">
|
|
// <info>
|
|
// Indicates the length of SPI transactions to this slave.</br>
|
|
// Valid transaction lengths are 1 through 64 bits. </br>
|
|
// This is not checked on FPGA and other values will </br>
|
|
// lead to undefined behavior.
|
|
// </info>
|
|
// </bitfield>
|
|
// <bitfield name="MISO_EDGE" range="27" initialvalue="0">
|
|
// <info>
|
|
// Controls the edge in which the MISO line is latched.</br>
|
|
// 0 = falling edge of SCLK.</br>
|
|
// 1 = rising edge of SCLK.
|
|
// </info>
|
|
// </bitfield>
|
|
// <bitfield name="MOSI_EDGE" range="28" initialvalue="0">
|
|
// <info>
|
|
// Controls the edge in which the MOSI line is updated.</br>
|
|
// 0 = falling edge of SCLK.</br>
|
|
// 1 = rising edge of SCLK.
|
|
// </info>
|
|
// </bitfield>
|
|
// </regtype>
|
|
// <register name="SPI_SLAVE_CONFIG" typename="SPI_SETUP" offset="0x00" count="4" options="--step 4">
|
|
// <info>Set of configuration registers for the supported slaves.
|
|
// Starting from FPGA compat number 10.1, the bit order for "Port A GPIO"
|
|
// and "Port B GPIO" matches the pin order of the "DIO" signals on the
|
|
// frontpanel connectors (which is the same order as the HDMI pin numbering
|
|
// with ground pins and pin 14 (HEC/ARC) left out). Up until FPGA compat
|
|
// number 10.0, software had to apply a mapping on software side to compensate
|
|
// for non-linear mapping in the FPGA.</info>
|
|
// </register>
|
|
// <register name="SPI_TRANSACTION_CONFIG" offset="0x10" size="32">
|
|
// <info>
|
|
// Controls clock rate and target for subsequent SPI transactions.
|
|
// </info>
|
|
// <bitfield name="SPI_CLK_DIV" range="0..15" initialvalue="0">
|
|
// <info> Controls the rate for subsequent SPI transactions. SCLK = DataClk/[(SPI_CLK_DIV+1)]</info>
|
|
// </bitfield>
|
|
// <bitfield name="SPI_SLAVE_SELECT" range="16..17" initialvalue="0"/>
|
|
// </register>
|
|
// <register name="SPI_TRANSACTION_LSB" offset="0x14" size="32" readable="false">
|
|
// <info>
|
|
// For SPI transactions with @.SPI_SLAVE_CONFIG.SPI_LENGTH > 32, this must be written
|
|
// before @.SPI_TRANSACTION_GO.
|
|
// </info>
|
|
// <bitfield name="SPI_DATA_LSB" range="0..31" initialvalue="0">
|
|
// <info> Left-aligned LSB payload for SPI transaction with @.SPI_SLAVE_CONFIG.SPI_LENGTH > 32.<br/>
|
|
// See @.SPI_TRANSACTION_GO for more information.</info>
|
|
// </bitfield>
|
|
// </register>
|
|
// <register name="SPI_TRANSACTION_GO" offset="0x18" size="32" readable="false">
|
|
// <info>
|
|
// Starts a SPI transaction. Does not check whether a previous transaction is still ongoing.
|
|
// If so, the running transaction may be corrupted.
|
|
// </info>
|
|
// <bitfield name="SPI_DATA" range="0..31" initialvalue="0">
|
|
// <info> Payload to be sent for the SPI transaction.<br/>
|
|
// If the payload is shorter than 32 bits, it must be left-aligned.
|
|
// The first transmitted bit is the MSB and data is shifted out to the left.<br/>
|
|
// If the desired payload is longer than 32 bits, the remaining LSBs
|
|
// must be written to @.SPI_TRANSACTION_LSB.SPI_DATA_LSB (left-aligned) before starting
|
|
// the transaction. </info>
|
|
// </bitfield>
|
|
// </register>
|
|
// <register name="SPI_STATUS" offset="0x1C" size="32" writable="false">
|
|
// <info>
|
|
// Contains the status of the SPI engine and the least-significant 31 bits of the response.
|
|
// Also read SPI_FULL_RESPONSE_MSB for bit 32 or for transactions longer than 32 bits.
|
|
// </info>
|
|
// <bitfield name="SPI_READY" range="31" initialvalue="0">
|
|
// <info> Indicates the SPI engine is ready to start a new SPI transaction. </info>
|
|
// </bitfield>
|
|
// <bitfield name="SPI_RESPONSE" range="0..30" initialvalue="0">
|
|
// <info> Records only the least-significant 31 bits of the last completed SPI response. </info>
|
|
// </bitfield>
|
|
// </register>
|
|
// <register name="SPI_FULL_RESPONSE_MSB" offset="0x20" size="32" writable="false">
|
|
// <info>
|
|
// Contains bits 62 through 31 of the last completed SPI response.
|
|
// For transactions shorter than 31 bits, the upper bits in this register are undefined.
|
|
// The regmap does not expose the most significant bit (bit 63) of the response.
|
|
// </info>
|
|
// <bitfield name="SPI_FULL_RESPONSE_MSB_DATA" range="0..31" initialvalue="0"/>
|
|
// </register>
|
|
// <register name="CONTROLLER_INFO" offset="0x24" size="32" writable="false">
|
|
// <info>
|
|
// Contains information pertaining this SPI controller block.
|
|
// </info>
|
|
// <bitfield name="SLAVE_COUNT" range="3..0">
|
|
// <info> Indicates the number SPI slaves configurable by the controller. </info>
|
|
// </bitfield>
|
|
// </register>
|
|
// </group>
|
|
//</regmap>
|
|
//XmlParse xml_off
|