mirror of
https://github.com/EttusResearch/uhd.git
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e6470cf8ce
Extend GPIO SPI transactions up to 64 bits and update the X4xx FPGA register map and RTL to support the new access width. Migrate the GPIO SPI register definitions to SystemVerilog. Add testbench for X4xx GPIO SPI module covering both exisiting 32bit functionality and added 64bit functionality. Separate TB Makefiles for X4xx and X410 implementation variant. Bump the FPGA compatibility number so host and MPM software can reject images that do not provide the required GPIO SPI register interface.
164 lines
7.6 KiB
Systemverilog
164 lines
7.6 KiB
Systemverilog
//-----------------------------------------------------------------------------
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// File: XmlSvPkgDIG_IFC_REGMAP.sv
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// Author: Autogenerated by XmlParse
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// Original Project: --
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// Date: --
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//-----------------------------------------------------------------------------
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// (c) 2026 National Instruments Corporation. All Rights Reserved.
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//-----------------------------------------------------------------------------
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// Purpose:
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// The constants in this file are autogenerated by XmlParse.
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//-----------------------------------------------------------------------------
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package XmlSvPkgDIG_IFC_REGMAP;
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//===============================================================================
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// A numerically ordered list of registers and their HDL source files
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//===============================================================================
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// SPI_SLAVE_CONFIG : 0x0 (x4xx_gpio_spi.sv)
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// SPI_TRANSACTION_CONFIG : 0x10 (x4xx_gpio_spi.sv)
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// SPI_TRANSACTION_LSB : 0x14 (x4xx_gpio_spi.sv)
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// SPI_TRANSACTION_GO : 0x18 (x4xx_gpio_spi.sv)
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// SPI_STATUS : 0x1C (x4xx_gpio_spi.sv)
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// SPI_FULL_RESPONSE_MSB : 0x20 (x4xx_gpio_spi.sv)
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// CONTROLLER_INFO : 0x24 (x4xx_gpio_spi.sv)
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//===============================================================================
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// Register Group SPI_OVER_GPIO_REGS
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//===============================================================================
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// SPI_SLAVE_CONFIG Register (from x4xx_gpio_spi.sv)
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localparam kSPI_SLAVE_CONFIGCount = 4; // Number of elements in array
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// SPI_TRANSACTION_CONFIG Register (from x4xx_gpio_spi.sv)
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localparam kSPI_TRANSACTION_CONFIG = 'h10; // Register Offset
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localparam kSPI_TRANSACTION_CONFIGSize = 32; // register width in bits
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localparam kSPI_TRANSACTION_CONFIGMask = 32'h3FFFF;
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localparam kSPI_CLK_DIVSize = 16; //SPI_TRANSACTION_CONFIG:SPI_CLK_DIV
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localparam kSPI_CLK_DIVMsb = 15; //SPI_TRANSACTION_CONFIG:SPI_CLK_DIV
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localparam kSPI_CLK_DIV = 0; //SPI_TRANSACTION_CONFIG:SPI_CLK_DIV
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localparam kSPI_SLAVE_SELECTSize = 2; //SPI_TRANSACTION_CONFIG:SPI_SLAVE_SELECT
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localparam kSPI_SLAVE_SELECTMsb = 17; //SPI_TRANSACTION_CONFIG:SPI_SLAVE_SELECT
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localparam kSPI_SLAVE_SELECT = 16; //SPI_TRANSACTION_CONFIG:SPI_SLAVE_SELECT
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typedef struct packed {
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logic [13:0] Rsvd31_18; // [31:18] 14 bit spacer
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logic [1:0] SPI_SLAVE_SELECT; // [17:16] 2 bit bitfield
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logic [15:0] SPI_CLK_DIV; // [15: 0] 16 bit bitfield
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} SPI_TRANSACTION_CONFIG;
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// SPI_TRANSACTION_LSB Register (from x4xx_gpio_spi.sv)
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localparam kSPI_TRANSACTION_LSB = 'h14; // Register Offset
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localparam kSPI_TRANSACTION_LSBSize = 32; // register width in bits
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localparam kSPI_TRANSACTION_LSBMask = 32'hFFFFFFFF;
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localparam kSPI_DATA_LSBSize = 32; //SPI_TRANSACTION_LSB:SPI_DATA_LSB
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localparam kSPI_DATA_LSBMsb = 31; //SPI_TRANSACTION_LSB:SPI_DATA_LSB
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localparam kSPI_DATA_LSB = 0; //SPI_TRANSACTION_LSB:SPI_DATA_LSB
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typedef struct packed {
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logic [31:0] SPI_DATA_LSB; // [31: 0] 32 bit bitfield
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} SPI_TRANSACTION_LSB;
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// SPI_TRANSACTION_GO Register (from x4xx_gpio_spi.sv)
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localparam kSPI_TRANSACTION_GO = 'h18; // Register Offset
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localparam kSPI_TRANSACTION_GOSize = 32; // register width in bits
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localparam kSPI_TRANSACTION_GOMask = 32'hFFFFFFFF;
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localparam kSPI_DATASize = 32; //SPI_TRANSACTION_GO:SPI_DATA
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localparam kSPI_DATAMsb = 31; //SPI_TRANSACTION_GO:SPI_DATA
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localparam kSPI_DATA = 0; //SPI_TRANSACTION_GO:SPI_DATA
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typedef struct packed {
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logic [31:0] SPI_DATA; // [31: 0] 32 bit bitfield
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} SPI_TRANSACTION_GO;
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// SPI_STATUS Register (from x4xx_gpio_spi.sv)
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localparam kSPI_STATUS = 'h1C; // Register Offset
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localparam kSPI_STATUSSize = 32; // register width in bits
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localparam kSPI_STATUSMask = 32'hFFFFFFFF;
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localparam kSPI_RESPONSESize = 31; //SPI_STATUS:SPI_RESPONSE
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localparam kSPI_RESPONSEMsb = 30; //SPI_STATUS:SPI_RESPONSE
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localparam kSPI_RESPONSE = 0; //SPI_STATUS:SPI_RESPONSE
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localparam kSPI_READYSize = 1; //SPI_STATUS:SPI_READY
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localparam kSPI_READYMsb = 31; //SPI_STATUS:SPI_READY
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localparam kSPI_READY = 31; //SPI_STATUS:SPI_READY
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typedef struct packed {
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logic SPI_READY; // [31:31] 1 bit bitfield
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logic [30:0] SPI_RESPONSE; // [30: 0] 31 bit bitfield
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} SPI_STATUS;
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// SPI_FULL_RESPONSE_MSB Register (from x4xx_gpio_spi.sv)
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localparam kSPI_FULL_RESPONSE_MSB = 'h20; // Register Offset
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localparam kSPI_FULL_RESPONSE_MSBSize = 32; // register width in bits
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localparam kSPI_FULL_RESPONSE_MSBMask = 32'hFFFFFFFF;
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localparam kSPI_FULL_RESPONSE_MSB_DATASize = 32; //SPI_FULL_RESPONSE_MSB:SPI_FULL_RESPONSE_MSB_DATA
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localparam kSPI_FULL_RESPONSE_MSB_DATAMsb = 31; //SPI_FULL_RESPONSE_MSB:SPI_FULL_RESPONSE_MSB_DATA
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localparam kSPI_FULL_RESPONSE_MSB_DATA = 0; //SPI_FULL_RESPONSE_MSB:SPI_FULL_RESPONSE_MSB_DATA
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typedef struct packed {
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logic [31:0] SPI_FULL_RESPONSE_MSB_DATA; // [31: 0] 32 bit bitfield
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} SPI_FULL_RESPONSE_MSB;
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// CONTROLLER_INFO Register (from x4xx_gpio_spi.sv)
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localparam kCONTROLLER_INFO = 'h24; // Register Offset
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localparam kCONTROLLER_INFOSize = 32; // register width in bits
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localparam kCONTROLLER_INFOMask = 32'hF;
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localparam kSLAVE_COUNTSize = 4; //CONTROLLER_INFO:SLAVE_COUNT
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localparam kSLAVE_COUNTMsb = 3; //CONTROLLER_INFO:SLAVE_COUNT
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localparam kSLAVE_COUNT = 0; //CONTROLLER_INFO:SLAVE_COUNT
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typedef struct packed {
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logic [27:0] Rsvd31_4; // [31: 4] 28 bit spacer
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logic [3:0] SLAVE_COUNT; // [ 3: 0] 4 bit bitfield
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} CONTROLLER_INFO;
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//===============================================================================
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// RegTypes
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//===============================================================================
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// SPI_SETUP Type (from x4xx_gpio_spi.sv)
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localparam kSPI_SETUPSize = 32;
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localparam kSPI_SETUPMask = 32'h1FFFFFFF;
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localparam kSLAVE_CLKSize = 5; //SPI_SETUP:SLAVE_CLK
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localparam kSLAVE_CLKMsb = 4; //SPI_SETUP:SLAVE_CLK
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localparam kSLAVE_CLK = 0; //SPI_SETUP:SLAVE_CLK
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localparam kSLAVE_MOSISize = 5; //SPI_SETUP:SLAVE_MOSI
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localparam kSLAVE_MOSIMsb = 9; //SPI_SETUP:SLAVE_MOSI
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localparam kSLAVE_MOSI = 5; //SPI_SETUP:SLAVE_MOSI
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localparam kSLAVE_MISOSize = 5; //SPI_SETUP:SLAVE_MISO
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localparam kSLAVE_MISOMsb = 14; //SPI_SETUP:SLAVE_MISO
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localparam kSLAVE_MISO = 10; //SPI_SETUP:SLAVE_MISO
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localparam kSLAVE_CSSize = 5; //SPI_SETUP:SLAVE_CS
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localparam kSLAVE_CSMsb = 19; //SPI_SETUP:SLAVE_CS
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localparam kSLAVE_CS = 15; //SPI_SETUP:SLAVE_CS
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localparam kSPI_LENGTHSize = 7; //SPI_SETUP:SPI_LENGTH
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localparam kSPI_LENGTHMsb = 26; //SPI_SETUP:SPI_LENGTH
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localparam kSPI_LENGTH = 20; //SPI_SETUP:SPI_LENGTH
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localparam kMISO_EDGESize = 1; //SPI_SETUP:MISO_EDGE
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localparam kMISO_EDGEMsb = 27; //SPI_SETUP:MISO_EDGE
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localparam kMISO_EDGE = 27; //SPI_SETUP:MISO_EDGE
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localparam kMOSI_EDGESize = 1; //SPI_SETUP:MOSI_EDGE
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localparam kMOSI_EDGEMsb = 28; //SPI_SETUP:MOSI_EDGE
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localparam kMOSI_EDGE = 28; //SPI_SETUP:MOSI_EDGE
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typedef struct packed {
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logic [2:0] Rsvd31_29; // [31:29] 3 bit spacer
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logic MOSI_EDGE; // [28:28] 1 bit bitfield
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logic MISO_EDGE; // [27:27] 1 bit bitfield
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logic [6:0] SPI_LENGTH; // [26:20] 7 bit bitfield
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logic [4:0] SLAVE_CS; // [19:15] 5 bit bitfield
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logic [4:0] SLAVE_MISO; // [14:10] 5 bit bitfield
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logic [4:0] SLAVE_MOSI; // [ 9: 5] 5 bit bitfield
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logic [4:0] SLAVE_CLK; // [ 4: 0] 5 bit bitfield
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} SPI_SETUP;
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// Return the offset of an element of register array kSPI_SLAVE_CONFIG
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function automatic integer kSPI_SLAVE_CONFIG (input integer i);
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begin
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kSPI_SLAVE_CONFIG = (i * 'h4) + 'h0;
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end
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endfunction
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endpackage : XmlSvPkgDIG_IFC_REGMAP
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