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41 lines
1.5 KiB
Verilog
41 lines
1.5 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module packet_verifier32
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(input clk, input reset, input clear,
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input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
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output [31:0] total, output [31:0] crc_err, output [31:0] seq_err, output [31:0] len_err);
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wire [7:0] ll_data;
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wire ll_sof, ll_eof, ll_src_rdy, ll_dst_rdy;
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fifo36_to_ll8 f36_to_ll8
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(.clk(clk), .reset(reset), .clear(clear),
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.f36_data(data_i), .f36_src_rdy_i(src_rdy_i), .f36_dst_rdy_o(dst_rdy_o),
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.ll_data(ll_data), .ll_sof(ll_sof), .ll_eof(ll_eof),
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.ll_src_rdy(ll_src_rdy), .ll_dst_rdy(ll_dst_rdy));
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packet_verifier pkt_ver
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(.clk(clk), .reset(reset), .clear(clear),
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.data_i(ll_data), .sof_i(ll_sof), .eof_i(ll_eof),
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.src_rdy_i(ll_src_rdy), .dst_rdy_o(ll_dst_rdy),
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.total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
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endmodule // packet_verifier32
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