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b4aeb78438
Added variants for the DDC/DUC blocks that can process multiple samples per cycle and can be used for bandwidths higher than 200Mhz. This new feature is integrated into the existing RFNoC DDC/DUC blocks. Depending on the Radio bandwidth specified for the USRP variant, the DxC blocks will instantiate the existing singlesample implementation(for FPGA image variants <= 200MHz) or instantiate the multisample implementation(for FPGA image variants > 200MHz). Co-authored-by: Niels Garibaldi <niels.steffen.garibaldi@emerson.com> Co-authored-by: André Zoch <andre.zoch@emerson.com> Co-authored-by: Meghana Halladamath <meghana.halladamath@emerson.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Max Köhler <max.koehler@emerson.com>
87 lines
3.0 KiB
Systemverilog
87 lines
3.0 KiB
Systemverilog
//
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// Copyright 2026 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: cic_destaircase_pipeline
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//
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// Description:
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//
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// Reverses the stagger introduced by cic_staircase_pipeline so that all
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// lanes are re-aligned to the same clock cycle.
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//
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// cic_staircase_pipeline delays lane k by k cycles.
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// This module delays lane k by (SPC-1-k) cycles, giving every lane a
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// uniform total latency of (SPC-1) clock-enabled cycles.
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//
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// out_data[0] = in_data[0] delayed SPC-1 cycles
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// out_data[k] = in_data[k] delayed SPC-1-k cycles
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// out_data[SPC-1] = in_data[SPC-1] (wire, 0 FFs)
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//
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// valid_in and valid_out are delayed according to lane 0. This is effectively
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// a delay by SPC-1 cycles.
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//
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// Parameters:
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// DATA_W : Bit width of each element.
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// SPC : Number of parallel lanes (samples per clock).
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//
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module cic_destaircase_pipeline #(
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parameter int DATA_W = 16,
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parameter int SPC = 8
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) (
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input logic clk,
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input logic rst,
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input logic en,
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input logic valid_in,
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input logic [SPC-1:0][DATA_W-1:0] in_data,
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output logic valid_out,
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output logic [SPC-1:0][DATA_W-1:0] out_data
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);
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// --------------------------------------------------------------------
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// Valid pipeline
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// --------------------------------------------------------------------
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// valid_pipeline[d] = valid_in delayed by d clock-enabled cycles.
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// valid_pipeline[0] is a wire (no register).
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logic valid_pipeline [SPC];
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assign valid_pipeline[0] = valid_in;
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for (genvar d = 1; d < SPC; d++) begin : gen_valid_pipeline
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always_ff @(posedge clk) begin : valid_ff
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if (rst) begin
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valid_pipeline[d] <= 1'b0;
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end else if (en) begin
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valid_pipeline[d] <= valid_pipeline[d-1];
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end
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end : valid_ff
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end : gen_valid_pipeline
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assign valid_out = valid_pipeline[SPC-1];
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// --------------------------------------------------------------------
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// Data pipeline
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// --------------------------------------------------------------------
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// pipeline[k][d] = in_data[k] delayed by d clock-enabled cycles.
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// pipeline[k][0] is a wire (no register).
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logic [DATA_W-1:0] pipeline [SPC][SPC];
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for (genvar k = 0; k < SPC; k++) begin : gen_pipeline_in
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assign pipeline[k][0] = in_data[k];
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end : gen_pipeline_in
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// Lane k needs (SPC-1-k) registers; lane SPC-1 needs 0 (wire only).
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for (genvar k = 0; k < SPC-1; k++) begin : gen_pipeline_lane
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for (genvar d = 1; d <= SPC-1-k; d++) begin : gen_pipeline_depth
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always_ff @(posedge clk) begin : pipeline_ff
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if (en) begin
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pipeline[k][d] <= pipeline[k][d-1];
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end
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end : pipeline_ff
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end : gen_pipeline_depth
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end : gen_pipeline_lane
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// Output: lane k taps the d = SPC-1-k entry.
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for (genvar k = 0; k < SPC; k++) begin : gen_out
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assign out_data[k] = pipeline[k][SPC-1-k];
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end : gen_out
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endmodule : cic_destaircase_pipeline
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