uhd/fpga/usrp3/lib/dsp/Makefile.srcs
Niels Garibaldi b4aeb78438 fpga: dsp: add wideband ddc and duc rfnoc blocks
Added variants for the DDC/DUC blocks that can process multiple
samples per cycle and can be used for bandwidths higher than
200Mhz.
This new feature is integrated into the existing RFNoC DDC/DUC
blocks. Depending on the Radio bandwidth specified for the USRP
variant, the DxC blocks will instantiate the existing singlesample
implementation(for FPGA image variants <= 200MHz) or instantiate
the multisample implementation(for FPGA image variants > 200MHz).

Co-authored-by: Niels Garibaldi <niels.steffen.garibaldi@emerson.com>
Co-authored-by: André Zoch <andre.zoch@emerson.com>
Co-authored-by: Meghana Halladamath <meghana.halladamath@emerson.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Max Köhler <max.koehler@emerson.com>
2026-08-05 08:43:42 +02:00

75 lines
1.5 KiB
Makefile

#
# Copyright 2013 Ettus Research LLC
# Copyright 2016 Ettus Research, a National Instruments Company
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
##################################################
# HB Filter Includes
##################################################
include $(BASE_DIR)/../lib/dsp/hb_filter/Makefile.srcs
##################################################
# DSP Sources
##################################################
DSP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/dsp/, \
acc.v \
add2_and_clip_reg.v \
add2_and_clip.v \
add2_and_round_reg.v \
add2_and_round.v \
add2_reg.v \
add2.v \
add_then_mac.v \
cic_decim.v \
cic_dec_shifter.v \
cic_interp.v \
cic_int_shifter.v \
cic_strober.v \
clip_reg.v \
clip.v \
cordic_stage.v \
cordic_z24.v \
ddc_chain.v \
duc_chain.v \
hb47_int.v \
hb_dec.v \
hb_interp.v \
mult_add_clip.v \
round_reg.v \
round_sd.v \
round.v \
rx_dcoffset.v \
rx_frontend.v \
sign_extend.v \
small_hb_dec.v \
small_hb_int.v \
srl.v \
tx_frontend.v \
variable_delay_line.v \
axi_fir_multisample_filter.sv \
axis_fir_ms_preload.sv \
complex_multiply.sv \
complex_multiply_iq.sv \
complex_multiply_stb.sv \
timed_complex_gain_regs.svh \
timed_complex_gain.sv \
utils/cic_utils_pkg.sv \
cic_integrator.sv \
cic_integrator_core.sv \
cic_staircase_pipeline.sv \
cic_destaircase_pipeline.sv \
dsp48_add3.sv \
dsp48_accum.sv \
dsp48_prefix_accum.sv \
cic_decimator.sv \
cic_interpolator.sv \
cic_comb_filter.sv \
cic_barrel_shift.sv \
cic_filter_decim.sv \
cic_filter_interp.sv \
))
DSP_SRCS += $(HB_FILTER_SRCS)