uhd/.ci/uhd-pipeline.yml

#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#

parameters:
  # Force enable/disable modules, examples:
  #
  # Force-enable/disable UHD builds...
  # ... for all OS:  uhd.build.all
  # ... for Linux:   uhd.build.linux
  # ... for Windows: uhd.build.windows
  # ... for macOS:   uhd.build.mac
  #
  # Force-enable/disable MPM builds...
  # ... for all devs: mpm.build.all
  #
  # Force-enable/disable FPGA images builds...
  # ... all FPGAs:   fpga.usrp3.all
  # ... E31X FPGAs:  fpga.usrp3.e31x
  # ... E320 FPGAs:  fpga.usrp3.e320
  # ... N3XX FPGAs:  fpga.usrp3.n3xx
  # ... X4XX FPGAs:  fpga.usrp3.x4xx
  # ... X410 FPGAs:  fpga.usrp3.x410
  # ... X440 FPGAs:  fpga.usrp3.x440
  #
  # Force-enable/disable tests...
  # ... Devtests: devtest.all
  # ... Streaming tests: hw.streaming.all
  # ... RF tests: hw.rf.all
  #
  # For more examples, see tools/changeset_testlist.yaml
- name: add_tests
  displayName: Force-enable modules
  type: string
  default: "uhd.build.all"
- name: remove_tests
  displayName: Force-disable modules
  type: string
  default: "none"
- name: release_binaries
  type: boolean
  displayName: Set release mode for installers
  default: false
- name: testLength
  type: string
  values:
  - 'smoke'
  - 'full'
  - 'stress'
  displayName: Test Length
  default: 'smoke'
- name: create_sbom
  type: boolean
  displayName: Create SBOM for filesystem images
  default: true
- name: build_sdk
  type: boolean
  displayName: Build embedded image SDKs
  default: false
- name: cache_sstate
  type: boolean
  displayName: Use sstate cache for embedded builds
  default: true
- name: build_e310_sg1
  type: boolean
  displayName: Build e310_sg1 image
  default: true
- name: build_e310_sg3
  type: boolean
  displayName: Build e310_sg3 image
  default: true
- name: build_e320
  type: boolean
  displayName: Build e320 image
  default: true
- name: build_n3xx
  type: boolean
  displayName: Build n3xx image
  default: true
- name: build_x4xx
  type: boolean
  displayName: Build x4xx image
  default: true
- name: ext_fpga
  type: boolean
  displayName: Use pipeline FPGA build
  default: true
  # This is the source of FPGA images only if they're not being built in this
  # pipeline. If they are being built, the source is the pipeline itself.
- name: fpga_imgs_source
  type: string
  values:
  - 'files.ettus.com (Public)'
  - 'Internal Repo'
  - 'Mono Pipeline'
  - 'Mono Pipeline PR'
  displayName: FPGA Images Source
  default: 'Mono Pipeline'
## FPGA parameters
- name: clean_ip_build
  type: boolean
  displayName: Clean IP Build
  default: true
- name: num_ip_jobs
  type: number
  default: 5
  displayName: Number of parallel IP jobs
- name: package_and_publish_images
  type: boolean
  displayName: Package & Publish Images
  default: true
- name: package_access
  type: string
  values:
  - 'Internal'
  - 'files.ettus.com (Public)'
  displayName: Published Package Access
  default: 'Internal'
- name: selected_streaming_tests
  type: string
  displayName: Streaming Tests Multi-Select (comma-separated)
  default: 'B206,B210,B310,X310_XG,X410_CG_400,X410_UC_200,X440_CG_400,X440_CG_1600'

trigger:
  batch: true
  branches:
    include:
    - master
    - UHD-*
  paths:
    include:
    - host
    - mpm
    - fpga
    - .ci
    - images/manifest.txt
    exclude:
    - .ci/docker
    - host/docs
    - host/LICENSE
    - host/README.md

pr: none

extends:
  template: templates/stages-uhd-pipeline.yml
  parameters:
    add_tests: ${{ parameters.add_tests }}
    remove_tests: ${{ parameters.remove_tests }}
    release_binaries: ${{ parameters.release_binaries }}
    testLength: ${{ parameters.testLength }}
    create_sbom: ${{ parameters.create_sbom }}
    build_sdk: ${{ parameters.build_sdk }}
    cache_sstate: ${{ parameters.cache_sstate }}
    build_e310_sg1: ${{ parameters.build_e310_sg1 }}
    build_e310_sg3: ${{ parameters.build_e310_sg3 }}
    build_e320: ${{ parameters.build_e320 }}
    build_n3xx: ${{ parameters.build_n3xx }}
    build_x4xx: ${{ parameters.build_x4xx }}
    fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
    # FPGA parameters
    clean_ip_build: ${{ parameters.clean_ip_build }}
    publish_int_files: true
    package_and_publish_images: ${{ parameters.package_and_publish_images }}
    package_access: ${{ parameters.package_access }}
    # Test parameters
    selected_streaming_tests: ${{ parameters.selected_streaming_tests }}