mirror of
https://github.com/EttusResearch/uhd.git
synced 2026-10-25 17:36:10 +00:00
87 lines
2.7 KiB
YAML
87 lines
2.7 KiB
YAML
parameters:
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- name: uhdArtifactSource
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type: string
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default: current
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- name: uhdFpgaArtifactSource
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type: string
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default: current
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- name: fpga_imgs_source
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type: string
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- name: extra_rf_test_args
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type: string
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default: ''
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- name: testLength
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type: string
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- name: runPyTest
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type: boolean
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default: true
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- name: runPyTestNonRF
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type: boolean
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default: true
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- name: runDevTest
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type: boolean
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default: true
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- name: runSystemImageTest
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type: boolean
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default: true
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- name: forceIQCorrections
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type: boolean
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default: false
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jobs:
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- ${{ if parameters.runPyTest }}:
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- template: templates/job-uhd-x4xx-hardware-tests.yml
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parameters:
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suiteName: 'dre_s175_x420_3'
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toolset: 'make'
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runPyTest: true
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runPyTestNonRF: false
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runDevTest: false
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runSystemImageTest: false
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forceIQCorrections: ${{ parameters.forceIQCorrections }}
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master_clock_rate: '245.76e6'
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uhdArtifactSource: ${{ parameters.uhdArtifactSource }}
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uhdFpgaArtifactSource: ${{ parameters.uhdFpgaArtifactSource }}
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fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
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extra_rf_test_args: '${{ parameters.extra_rf_test_args }}'
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testLength: '${{ parameters.testLength }}'
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dutMatrix:
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dre_s175-x420-3:
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dutName: 'dre_s175-x420-3'
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dutType: 'x4xx'
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devtestPattern: 'x420'
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dutFPGA: 'CG_1000'
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dutEmbeddedImagesArtifact: 'x4xx-images'
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uartSerial: '$(x420_uartSerial)'
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pipelineAgent: dre-s175-x420-3
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pytestAtsConfig: ec21_ats
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pytestDUT: 'x420'
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sfp0ip: '$(x420_dutAddr)'
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- ${{ if or(parameters.runPyTestNonRF, parameters.runDevTest, parameters.runSystemImageTest) }}:
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- template: templates/job-uhd-x4xx-hardware-tests.yml
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parameters:
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suiteName: 'dre_s175_x420_4'
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toolset: 'make'
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runPyTest: false
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runPyTestNonRF: ${{ parameters.runPyTestNonRF }}
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runDevTest: ${{ parameters.runDevTest }}
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runSystemImageTest: ${{ parameters.runSystemImageTest }}
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master_clock_rate: '245.76e6'
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uhdArtifactSource: ${{ parameters.uhdArtifactSource }}
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uhdFpgaArtifactSource: ${{ parameters.uhdFpgaArtifactSource }}
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fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
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extra_rf_test_args: '${{ parameters.extra_rf_test_args }}'
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testLength: '${{ parameters.testLength }}'
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dutMatrix:
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dre_s175-x420-4:
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dutName: 'dre_s175-x420-4'
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dutType: 'x4xx'
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devtestPattern: 'x420'
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dutFPGA: 'CG_1000'
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dutEmbeddedImagesArtifact: 'x4xx-images'
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uartSerial: '$(x420_uartSerial)'
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pipelineAgent: dre-s175-x420-4
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pytestAtsConfig: dre_s175_ats
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pytestDUT: 'x420'
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sfp0ip: '$(x420_dutAddr)'
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