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- Switched to FPGA SPI engine - Moved firmware AD9361 driver to UHD - Bumped FW compat to 5, FPGA compat to 4 - Known Issue: AD9361 SPI rate is too slow
57 lines
1.4 KiB
C++
57 lines
1.4 KiB
C++
//
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// Copyright 2014 Ettus Research LLC
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//
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#include <ad9361_client.h>
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double ad9361_client_get_band_edge(ad9361_product_t product, frequency_band_t band)
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{
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switch (product) {
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default:
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switch (band) {
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case AD9361_RX_BAND0: return 2.2e9;
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case AD9361_RX_BAND1: return 4.0e9;
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case AD9361_TX_BAND0: return 2.5e9;
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default: return 0;
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}
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}
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}
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clocking_mode_t ad9361_client_get_clocking_mode(ad9361_product_t product)
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{
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switch (product) {
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case AD9361_B200:
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return AD9361_XTAL_N_CLK_PATH;
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default:
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return AD9361_XTAL_N_CLK_PATH;
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}
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}
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digital_interface_mode_t ad9361_client_get_digital_interface_mode(ad9361_product_t product)
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{
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switch (product) {
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case AD9361_B200: return AD9361_DDR_FDD_LVCMOS;
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default: return AD9361_DDR_FDD_LVCMOS;
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}
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}
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digital_interface_delays_t ad9361_client_get_digital_interface_timing(ad9361_product_t product)
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{
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digital_interface_delays_t delays;
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switch (product) {
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case AD9361_B200:
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delays.rx_clk_delay = 0;
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delays.rx_data_delay = 0xF;
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delays.tx_clk_delay = 0;
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delays.tx_data_delay = 0xF;
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break;
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default:
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delays.rx_clk_delay = 0;
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delays.rx_data_delay = 0;
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delays.tx_clk_delay = 0;
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delays.tx_data_delay = 0;
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break;
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}
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return delays;
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}
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