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86 lines
2.5 KiB
Verilog
86 lines
2.5 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Split packets from a fifo based interface so it goes out identically on two interfaces
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module splitter36
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(
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input clk, input rst, input clr,
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input [35:0] inp_data, input inp_valid, output inp_ready,
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output [35:0] out0_data, output out0_valid, input out0_ready,
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output [35:0] out1_data, output out1_valid, input out1_ready
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);
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localparam STATE_COPY_BOTH = 0;
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localparam STATE_COPY_ZERO = 1;
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localparam STATE_COPY_ONE = 2;
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reg [1:0] state;
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reg [35:0] data_reg;
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assign out0_data = (state == STATE_COPY_BOTH)? inp_data : data_reg;
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assign out1_data = (state == STATE_COPY_BOTH)? inp_data : data_reg;
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assign out0_valid =
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(state == STATE_COPY_BOTH)? inp_valid : (
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(state == STATE_COPY_ZERO)? 1'b1 : (
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1'b0));
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assign out1_valid =
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(state == STATE_COPY_BOTH)? inp_valid : (
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(state == STATE_COPY_ONE)? 1'b1 : (
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1'b0));
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assign inp_ready = (state == STATE_COPY_BOTH)? (out0_ready | out1_ready) : 1'b0;
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always @(posedge clk)
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if (rst | clr) begin
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state <= STATE_COPY_BOTH;
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end
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else begin
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case (state)
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STATE_COPY_BOTH: begin
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if ((out0_valid & out0_ready) & ~(out1_valid & out1_ready)) begin
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state <= STATE_COPY_ONE;
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end
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else if (~(out0_valid & out0_ready) & (out1_valid & out1_ready)) begin
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state <= STATE_COPY_ZERO;
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end
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data_reg <= inp_data;
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end
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STATE_COPY_ZERO: begin
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if (out0_valid & out0_ready) begin
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state <= STATE_COPY_BOTH;
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end
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end
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STATE_COPY_ONE: begin
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if (out1_valid & out1_ready) begin
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state <= STATE_COPY_BOTH;
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end
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end
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endcase //state
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end
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endmodule //splitter36
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