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59 lines
2.6 KiB
Verilog
59 lines
2.6 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module fifo_2clock_cascade
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#(parameter WIDTH=32, SIZE=9)
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(input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o,
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output [15:0] space, output [15:0] short_space,
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input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i,
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output [15:0] occupied, output [15:0] short_occupied,
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input arst);
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wire [WIDTH-1:0] data_int1, data_int2;
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wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2;
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wire [SIZE-1:0] level_wclk, level_rclk;
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wire [4:0] s1_space, s1_occupied, s2_space, s2_occupied;
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wire [15:0] l_space, l_occupied;
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fifo_short #(.WIDTH(WIDTH)) shortfifo
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(.clk(wclk), .reset(arst), .clear(0),
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.datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
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.dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1),
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.space(s1_space), .occupied(s1_occupied) );
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fifo_2clock #(.WIDTH(WIDTH),.SIZE(SIZE)) fifo_2clock
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(.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .space(l_space),
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.rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .occupied(l_occupied),
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.arst(arst) );
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fifo_short #(.WIDTH(WIDTH)) shortfifo2
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(.clk(rclk), .reset(arst), .clear(0),
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.datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
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.dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
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.space(s2_space), .occupied(s2_occupied));
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// Be conservative -- Only advertise space from input side of fifo, occupied from output side
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assign space = {11'b0,s1_space} + l_space;
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assign occupied = {11'b0,s2_occupied} + l_occupied;
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// For the fifo_extram, we only want to know the immediately adjacent space
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assign short_space = {11'b0,s1_space};
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assign short_occupied = {11'b0,s2_occupied};
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endmodule // fifo_2clock_cascade
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