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https://github.com/EttusResearch/uhd.git
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ac896f0224
The mock RFNoC nodes that were previously only part of UHD are now part of the public headers (however, the mock nodes are not compiled as part of UHD). This makes them available to out-of-tree RFNoC modules that want to write unit tests for their block controllers.
364 lines
15 KiB
C++
364 lines
15 KiB
C++
//
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// Copyright 2019 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: GPL-3.0-or-later
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//
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#include <uhd/rfnoc/actions.hpp>
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#include <uhd/rfnoc/defaults.hpp>
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#include <uhd/rfnoc/detail/graph.hpp>
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#include <uhd/rfnoc/mock_block.hpp>
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#include <uhd/rfnoc/mock_nodes.hpp>
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#include <uhd/rfnoc/multichan_register_iface.hpp>
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#include <uhd/rfnoc/node_accessor.hpp>
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#include <uhd/rfnoc/register_iface_holder.hpp>
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#include <uhd/rfnoc/siggen_block_control.hpp>
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#include <uhd/utils/math.hpp>
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#include <uhdlib/utils/narrow.hpp>
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#include <boost/test/unit_test.hpp>
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#include <iostream>
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using namespace uhd::rfnoc;
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using namespace uhd::rfnoc::test;
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// Redeclare this here, since it's only defined outside of UHD_API
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noc_block_base::make_args_t::~make_args_t() = default;
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constexpr size_t NUM_PORTS = 4;
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constexpr size_t DEFAULT_MTU = 8000;
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/*
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* This class extends mock_reg_iface_t, handling three particular registers
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*/
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class siggen_mock_reg_iface_t : public mock_reg_iface_t
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{
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public:
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siggen_mock_reg_iface_t(size_t num_ports)
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: _num_ports(num_ports)
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, enables(_num_ports, false)
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, spps(_num_ports, 0)
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, waveforms(_num_ports, siggen_waveform::CONSTANT)
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, gains(_num_ports, 0)
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, constants(_num_ports, 0)
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, phase_increments(_num_ports, 0)
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, phasors(_num_ports, 0)
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{
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}
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void _poke_cb(
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uint32_t addr, uint32_t data, uhd::time_spec_t /*time*/, bool /*ack*/) override
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{
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const size_t port = addr / siggen_block_control::REG_BLOCK_SIZE;
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if (port >= _num_ports) {
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throw uhd::assertion_error("Invalid port index");
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}
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const size_t offset = addr % siggen_block_control::REG_BLOCK_SIZE;
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if (offset == siggen_block_control::REG_ENABLE_OFFSET) {
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enables[port] = (data > 0);
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} else if (offset == siggen_block_control::REG_SPP_OFFSET) {
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spps[port] = data;
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} else if (offset == siggen_block_control::REG_WAVEFORM_OFFSET) {
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waveforms[port] = static_cast<siggen_waveform>(data);
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} else if (offset == siggen_block_control::REG_GAIN_OFFSET) {
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gains[port] = data;
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} else if (offset == siggen_block_control::REG_CONSTANT_OFFSET) {
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constants[port] = data;
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} else if (offset == siggen_block_control::REG_PHASE_INC_OFFSET) {
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phase_increments[port] = data;
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} else if (offset == siggen_block_control::REG_CARTESIAN_OFFSET) {
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phasors[port] = data;
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} else {
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throw uhd::assertion_error("Invalid write to out of bounds offset");
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}
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}
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void _peek_cb(uint32_t addr, uhd::time_spec_t /*time*/) override
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{
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const size_t port = addr / siggen_block_control::REG_BLOCK_SIZE;
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if (port >= _num_ports) {
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throw uhd::assertion_error("Invalid port index");
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}
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const size_t offset = addr % siggen_block_control::REG_BLOCK_SIZE;
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if (offset == siggen_block_control::REG_ENABLE_OFFSET) {
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read_memory[addr] = enables[port] ? 1 : 0;
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} else if (offset == siggen_block_control::REG_SPP_OFFSET) {
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read_memory[addr] = spps[port];
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} else if (offset == siggen_block_control::REG_WAVEFORM_OFFSET) {
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read_memory[addr] = static_cast<uint32_t>(waveforms[port]);
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} else if (offset == siggen_block_control::REG_GAIN_OFFSET) {
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read_memory[addr] = gains[port];
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} else if (offset == siggen_block_control::REG_CONSTANT_OFFSET) {
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read_memory[addr] = constants[port];
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} else if (offset == siggen_block_control::REG_PHASE_INC_OFFSET) {
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read_memory[addr] = phase_increments[port];
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} else if (offset == siggen_block_control::REG_CARTESIAN_OFFSET) {
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read_memory[addr] = phasors[port];
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} else {
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throw uhd::assertion_error("Invalid read from out of bounds offset");
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}
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}
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template <class T>
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static const T clamp(const double v)
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{
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constexpr T min_t = std::numeric_limits<T>::min();
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constexpr T max_t = std::numeric_limits<T>::max();
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return (v < min_t) ? min_t : (v > max_t) ? max_t : T(v);
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}
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static uint32_t gain_to_register(double gain)
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{
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const int16_t gain_fp = clamp<int16_t>(gain * 32768.0);
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return static_cast<uint32_t>(gain_fp) & 0xffff;
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}
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static uint32_t constant_to_register(std::complex<double> constant)
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{
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const int16_t constant_i_fp = clamp<int16_t>(constant.real() * 32768.0);
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const int16_t constant_q_fp = clamp<int16_t>(constant.imag() * 32768.0);
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return (uint32_t(constant_i_fp) << 16) | (uint32_t(constant_q_fp) & 0xffff);
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}
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static uint32_t phase_increment_to_register(double phase_inc)
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{
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const int16_t phase_inc_scaled_rads_fp =
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clamp<int16_t>((phase_inc / uhd::math::PI) * 8192.0);
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return static_cast<uint32_t>(phase_inc_scaled_rads_fp) & 0xffff;
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}
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static uint32_t phasor_to_register(std::complex<double> phasor)
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{
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phasor /= 1.164435344782938; /* CORDIC scale value--see siggen_block_control */
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const int16_t phasor_i_fp = clamp<int16_t>(phasor.real() * 32767.0);
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const int16_t phasor_q_fp = clamp<int16_t>(phasor.imag() * 32767.0);
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return (uint32_t(phasor_i_fp) << 16) | (uint32_t(phasor_q_fp) & 0xffff);
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}
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private:
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const size_t _num_ports;
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public:
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std::vector<bool> enables;
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std::vector<uint32_t> spps;
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std::vector<siggen_waveform> waveforms;
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std::vector<uint32_t> gains;
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std::vector<uint32_t> constants;
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std::vector<uint32_t> phase_increments;
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std::vector<uint32_t> phasors;
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};
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/*
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* siggen_block_fixture is a class which is instantiated before each test
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* case is run. It sets up the block container, mock register interface,
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* and siggen_block_control object, all of which are accessible to the test
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* case. The instance of the object is destroyed at the end of each test
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* case.
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*/
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struct siggen_block_fixture
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{
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siggen_block_fixture()
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: reg_iface(std::make_shared<siggen_mock_reg_iface_t>(NUM_PORTS))
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, block_container(get_mock_block(SIGGEN_BLOCK,
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NUM_PORTS,
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NUM_PORTS,
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uhd::device_addr_t(),
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DEFAULT_MTU,
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ANY_DEVICE,
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reg_iface))
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, test_siggen(block_container.get_block<siggen_block_control>())
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{
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node_accessor.init_props(test_siggen.get());
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}
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std::shared_ptr<siggen_mock_reg_iface_t> reg_iface;
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mock_block_container block_container;
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std::shared_ptr<siggen_block_control> test_siggen;
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node_accessor_t node_accessor{};
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};
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/*
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* This test case ensures that the hardware is programmed correctly with
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* defaults when the siggen block is constructed.
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*/
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BOOST_FIXTURE_TEST_CASE(siggen_test_construction, siggen_block_fixture)
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{
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for (size_t port = 0; port < NUM_PORTS; port++) {
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BOOST_CHECK_EQUAL(reg_iface->enables.at(port), 0);
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BOOST_CHECK(reg_iface->waveforms.at(port) == siggen_waveform::CONSTANT);
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BOOST_CHECK_EQUAL(
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reg_iface->gains.at(port), siggen_mock_reg_iface_t::gain_to_register(1.0));
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BOOST_CHECK_EQUAL(reg_iface->constants.at(port),
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siggen_mock_reg_iface_t::constant_to_register({1.0, 1.0}));
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BOOST_CHECK_EQUAL(reg_iface->phase_increments.at(port),
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siggen_mock_reg_iface_t::phase_increment_to_register(1.0));
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BOOST_CHECK_EQUAL(reg_iface->phasors.at(port),
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siggen_mock_reg_iface_t::phasor_to_register({0.0, 0.0}));
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constexpr int bpi = 4; // sc16 has 4 bytes per item
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const int expected_spp =
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test_siggen->get_max_payload_size({res_source_info::OUTPUT_EDGE, port}) / bpi;
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BOOST_CHECK_EQUAL(reg_iface->spps.at(port), expected_spp);
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}
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}
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/*
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* This test case exercises the API and ensures that the registers are
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* programmed appropriately.
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*/
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BOOST_FIXTURE_TEST_CASE(siggen_test_api, siggen_block_fixture)
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{
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for (size_t port = 0; port < NUM_PORTS; port++) {
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test_siggen->set_enable(true, port);
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BOOST_CHECK_EQUAL(reg_iface->enables.at(port), 1);
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BOOST_CHECK_EQUAL(test_siggen->get_enable(port), true);
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// Set constant mode on the function generator, and then make sure
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// that the gain register stays fixed at 1 and that changing the
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// amplitude has no effect on the register or the attribute value
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// (which should always return 1 in this mode).
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const double amplitude = 0.25 + (port * 0.1);
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test_siggen->set_waveform(siggen_waveform::CONSTANT, port);
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BOOST_CHECK(reg_iface->waveforms.at(port) == siggen_waveform::CONSTANT);
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BOOST_CHECK(test_siggen->get_waveform(port) == siggen_waveform::CONSTANT);
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test_siggen->set_amplitude(amplitude, port);
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BOOST_CHECK_EQUAL(
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reg_iface->gains.at(port), siggen_mock_reg_iface_t::gain_to_register(1.0));
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BOOST_CHECK_EQUAL(test_siggen->get_amplitude(port), 1.0);
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// Set sine wave mode on the function generator, and then make sure
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// that the gain register stays fixed at 1, but that the Cartesian
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// register changes to reflect the desired sinusoidal amplitude.
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test_siggen->set_waveform(siggen_waveform::SINE_WAVE, port);
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BOOST_CHECK(reg_iface->waveforms.at(port) == siggen_waveform::SINE_WAVE);
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test_siggen->set_amplitude(amplitude, port);
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BOOST_CHECK_EQUAL(
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reg_iface->gains.at(port), siggen_mock_reg_iface_t::gain_to_register(1.0));
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BOOST_CHECK_EQUAL(reg_iface->phasors.at(port),
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siggen_mock_reg_iface_t::phasor_to_register({amplitude, 0.0}));
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BOOST_CHECK_EQUAL(test_siggen->get_amplitude(port), amplitude);
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// Set noise mode on the function generator, and then make sure
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// that the gain register changes according to the amplitude.
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test_siggen->set_waveform(siggen_waveform::NOISE, port);
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BOOST_CHECK(reg_iface->waveforms.at(port) == siggen_waveform::NOISE);
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BOOST_CHECK(test_siggen->get_waveform(port) == siggen_waveform::NOISE);
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test_siggen->set_amplitude(amplitude, port);
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BOOST_CHECK_EQUAL(reg_iface->gains.at(port),
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siggen_mock_reg_iface_t::gain_to_register(amplitude));
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BOOST_CHECK_EQUAL(test_siggen->get_amplitude(port), amplitude);
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const std::complex<double> constant{-0.5 - (port * 0.05), 0.5 + (port * 0.05)};
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test_siggen->set_constant(constant, port);
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BOOST_CHECK_EQUAL(reg_iface->constants.at(port),
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siggen_mock_reg_iface_t::constant_to_register(constant));
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BOOST_CHECK_EQUAL(test_siggen->get_constant(port), constant);
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const double phase_inc = (port * uhd::math::PI / 16.0);
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test_siggen->set_sine_phase_increment(phase_inc, port);
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BOOST_CHECK_EQUAL(reg_iface->phase_increments.at(port),
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siggen_mock_reg_iface_t::phase_increment_to_register(phase_inc));
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BOOST_CHECK_EQUAL(test_siggen->get_sine_phase_increment(port), phase_inc);
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const double freq = 1000 + (100 * port);
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const double samp_rate = 1e6;
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test_siggen->set_sine_frequency(freq, samp_rate, port);
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const double calculated_phase_inc = freq / samp_rate * 2.0 * uhd::math::PI;
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BOOST_CHECK_EQUAL(reg_iface->phase_increments.at(port),
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siggen_mock_reg_iface_t::phase_increment_to_register(calculated_phase_inc));
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BOOST_CHECK_EQUAL(
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test_siggen->get_sine_phase_increment(port), calculated_phase_inc);
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size_t spp = 100 + (200 * port);
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test_siggen->set_samples_per_packet(spp, port);
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BOOST_CHECK_EQUAL(reg_iface->spps.at(port), spp);
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BOOST_CHECK_EQUAL(test_siggen->get_samples_per_packet(port), spp);
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}
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}
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/*
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* This test case exercises the range checking performed on the siggen
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* settings, ensuring that the appropriate exception is thrown when out of
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* range.
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*/
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BOOST_FIXTURE_TEST_CASE(siggen_test_ranges, siggen_block_fixture)
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{
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for (size_t port = 0; port < NUM_PORTS; port++) {
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BOOST_CHECK_THROW(
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test_siggen->set_property<int>("waveform", 100, port), uhd::value_error);
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const double bad_amplitude = 100 + (port * 100);
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// I got a bad amplitude!
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BOOST_CHECK_THROW(
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test_siggen->set_amplitude(bad_amplitude, port), uhd::value_error);
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BOOST_CHECK_THROW(
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test_siggen->set_amplitude(-bad_amplitude, port), uhd::value_error);
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const std::complex<double> bad_constant_i{-100.0 + (port * 100), 0.1};
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BOOST_CHECK_THROW(
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test_siggen->set_constant(bad_constant_i, port), uhd::value_error);
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BOOST_CHECK_THROW(
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test_siggen->set_constant(-bad_constant_i, port), uhd::value_error);
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const std::complex<double> bad_constant_q{-0.1, 100.0 + (port * 100)};
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BOOST_CHECK_THROW(
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test_siggen->set_constant(bad_constant_q, port), uhd::value_error);
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BOOST_CHECK_THROW(
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test_siggen->set_constant(-bad_constant_q, port), uhd::value_error);
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const double bad_phase_inc = 5 * uhd::math::PI;
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BOOST_CHECK_THROW(
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test_siggen->set_sine_phase_increment(bad_phase_inc, port), uhd::value_error);
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BOOST_CHECK_THROW(test_siggen->set_sine_phase_increment(-bad_phase_inc, port),
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uhd::value_error);
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const double bad_samp_rate_zero = 0.0;
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BOOST_CHECK_THROW(test_siggen->set_sine_frequency(10.0, bad_samp_rate_zero, port),
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uhd::value_error);
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const double bad_samp_rate = 30.0 + (port * 10);
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const double bad_freq = bad_samp_rate * 10.0;
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BOOST_CHECK_THROW(test_siggen->set_sine_frequency(bad_freq, bad_samp_rate, port),
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uhd::value_error);
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}
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}
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/*
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* This test case exercises the coercion of the SPP parameter to ensure that
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* it does not surpass the MTU.
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*/
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BOOST_FIXTURE_TEST_CASE(siggen_test_spp_coercion, siggen_block_fixture)
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{
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const size_t max_samps =
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(DEFAULT_MTU - test_siggen->get_chdr_hdr_len()) / 4 /* bytes/samp */;
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const size_t too_high_spp = max_samps + 10;
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test_siggen->set_samples_per_packet(too_high_spp, 0);
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BOOST_CHECK_EQUAL(test_siggen->get_samples_per_packet(0), max_samps);
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}
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/*
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* This test case ensures that the siggen block controller can be added
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* to a graph.
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*/
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BOOST_FIXTURE_TEST_CASE(siggen_test_graph, siggen_block_fixture)
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{
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detail::graph_t graph{};
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detail::graph_t::graph_edge_t edge_info{
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0, 0, detail::graph_t::graph_edge_t::DYNAMIC, true};
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mock_terminator_t mock_sink_term(NUM_PORTS, {}, "MOCK_SINK");
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mock_sink_term.set_edge_property<std::string>(
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"type", "sc16", {res_source_info::INPUT_EDGE, 0});
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UHD_LOG_INFO("TEST", "Creating graph...");
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for (size_t port = 0; port < NUM_PORTS; port++) {
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graph.connect(test_siggen.get(),
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&mock_sink_term,
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{port, port, detail::graph_t::graph_edge_t::DYNAMIC, true});
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}
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UHD_LOG_INFO("TEST", "Committing graph...");
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graph.commit();
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UHD_LOG_INFO("TEST", "Commit complete.");
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}
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