mirror of
https://github.com/EttusResearch/uhd.git
synced 2026-10-25 17:36:10 +00:00
a18579e3e5
Co-authored-by: Virendra Kakade <virendra.kakade@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Javier Valenzuela <javier.j.valenzuela@emerson.com>
142 lines
4.5 KiB
YAML
142 lines
4.5 KiB
YAML
#
|
|
# Copyright 2025 Ettus Research, a National Instruments Brand
|
|
#
|
|
# SPDX-License-Identifier: GPL-3.0-or-later
|
|
#
|
|
# Description:
|
|
#
|
|
# This template defines a stages-based pipeline for building all FPGA bitfiles.
|
|
#
|
|
|
|
parameters:
|
|
## Optional parameters
|
|
# Option to ignore cached artifacts (if available) and perform
|
|
# a clean IP build.
|
|
- name: clean_ip_build
|
|
type: boolean
|
|
default: false
|
|
# Number of parallel jobs to use for IP build
|
|
- name: num_ip_jobs
|
|
type: number
|
|
default: 5
|
|
# Option to publish intermediate files
|
|
- name: publish_int_files
|
|
type: boolean
|
|
default: false
|
|
# Package and publish images
|
|
- name: package_and_publish_images
|
|
type: boolean
|
|
default: true
|
|
# Package access in the SDR server ('Internal' or 'Public')
|
|
- name: package_access
|
|
type: string
|
|
default: 'Internal'
|
|
# From where to pull FPGA bitfiles if we're not building them
|
|
- name: fpga_imgs_source
|
|
type: string
|
|
default: 'Mono Pipeline'
|
|
## Device-specific parameters
|
|
- name: x410_targets_matrix
|
|
type: object
|
|
default: {}
|
|
- name: x420_targets_matrix
|
|
type: object
|
|
default: {}
|
|
- name: x440_targets_matrix
|
|
type: object
|
|
default: {}
|
|
- name: additional_setup_steps
|
|
type: stepList
|
|
default: []
|
|
- name: rfnoc_include_dir
|
|
type: string
|
|
default: ""
|
|
displayName: RFNoC OOT module path
|
|
|
|
|
|
stages:
|
|
### START: X400 stages
|
|
|
|
- template: ../devices/job-build-fpga-x400.yml
|
|
parameters:
|
|
clean_ip_build: ${{ parameters.clean_ip_build }}
|
|
publish_int_files: ${{ parameters.publish_int_files }}
|
|
package_and_publish_images: ${{ parameters.package_and_publish_images }}
|
|
package_access: ${{ parameters.package_access }}
|
|
x410_targets_matrix: ${{ parameters.x410_targets_matrix }}
|
|
x420_targets_matrix: ${{ parameters.x420_targets_matrix }}
|
|
x440_targets_matrix: ${{ parameters.x440_targets_matrix }}
|
|
fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
|
|
additional_setup_steps: ${{ parameters.additional_setup_steps }}
|
|
rfnoc_include_dir: ${{ parameters.rfnoc_include_dir }}
|
|
|
|
### END: X400 stages
|
|
|
|
### START: X3x0 stages
|
|
|
|
- template: ../devices/job-build-fpga-x300.yml
|
|
parameters:
|
|
clean_ip_build: ${{ parameters.clean_ip_build }}
|
|
publish_int_files: ${{ parameters.publish_int_files }}
|
|
package_and_publish_images: ${{ parameters.package_and_publish_images }}
|
|
package_access: ${{ parameters.package_access }}
|
|
fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
|
|
additional_setup_steps: ${{ parameters.additional_setup_steps }}
|
|
rfnoc_include_dir: ${{ parameters.rfnoc_include_dir }}
|
|
|
|
### END: X3x0 stages
|
|
|
|
### START: N3xx stages
|
|
|
|
- template: ../devices/job-build-fpga-n3xx.yml
|
|
parameters:
|
|
clean_ip_build: ${{ parameters.clean_ip_build }}
|
|
publish_int_files: ${{ parameters.publish_int_files }}
|
|
package_and_publish_images: ${{ parameters.package_and_publish_images }}
|
|
package_access: ${{ parameters.package_access }}
|
|
fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
|
|
additional_setup_steps: ${{ parameters.additional_setup_steps }}
|
|
rfnoc_include_dir: ${{ parameters.rfnoc_include_dir }}
|
|
|
|
### END: N3xx stages
|
|
|
|
### START: E31x stages
|
|
|
|
- template: ../devices/job-build-fpga-e31x.yml
|
|
parameters:
|
|
clean_ip_build: ${{ parameters.clean_ip_build }}
|
|
publish_int_files: ${{ parameters.publish_int_files }}
|
|
package_and_publish_images: ${{ parameters.package_and_publish_images }}
|
|
package_access: ${{ parameters.package_access }}
|
|
fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
|
|
additional_setup_steps: ${{ parameters.additional_setup_steps }}
|
|
rfnoc_include_dir: ${{ parameters.rfnoc_include_dir }}
|
|
|
|
### END: E31x stages
|
|
|
|
### START: E320 stages
|
|
|
|
- template: ../devices/job-build-fpga-e320.yml
|
|
parameters:
|
|
clean_ip_build: ${{ parameters.clean_ip_build }}
|
|
publish_int_files: ${{ parameters.publish_int_files }}
|
|
package_and_publish_images: ${{ parameters.package_and_publish_images }}
|
|
package_access: ${{ parameters.package_access }}
|
|
fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
|
|
additional_setup_steps: ${{ parameters.additional_setup_steps }}
|
|
rfnoc_include_dir: ${{ parameters.rfnoc_include_dir }}
|
|
|
|
### END: E320 stages
|
|
|
|
### START: B310 stages
|
|
|
|
- template: ../devices/job-build-fpga-b310.yml
|
|
parameters:
|
|
clean_ip_build: ${{ parameters.clean_ip_build }}
|
|
publish_int_files: ${{ parameters.publish_int_files }}
|
|
package_and_publish_images: ${{ parameters.package_and_publish_images }}
|
|
package_access: ${{ parameters.package_access }}
|
|
fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
|
|
|
|
### END: B310 stages
|