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a18579e3e5
Co-authored-by: Virendra Kakade <virendra.kakade@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Javier Valenzuela <javier.j.valenzuela@emerson.com>
109 lines
3.2 KiB
YAML
109 lines
3.2 KiB
YAML
#
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# Copyright 2025 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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#
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# This template defines a stages-based pipeline for building B310 FPGA
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# targets.
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#
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# See https://aka.ms/yaml for pipeline YAML documentation.
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#
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parameters:
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## Optional parameters
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# Option to ignore cached artifacts (if available) and perform
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# a clean IP build.
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- name: clean_ip_build
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type: boolean
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default: false
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# Number of parallel jobs to use for IP build
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- name: num_ip_jobs
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type: number
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default: 5
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# Option to publish intermediate files
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- name: publish_int_files
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type: boolean
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default: false
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# Package and publish images
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- name: package_and_publish_images
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type: boolean
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default: true
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# Package access in the SDR server ('Internal' or 'Public')
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- name: package_access
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type: string
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default: 'Internal'
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# From where to pull FPGA bitfiles if we're not building them
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- name: fpga_imgs_source
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type: string
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default: 'Mono Pipeline'
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# B310 FPGA targets to build
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- name: b310_full_targets_matrix
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type: object
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default:
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B310_REPLAY:
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image_core: b310_replay_rfnoc_image_core.yml
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target_name: B310
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image_core_name: usrp_b310_fpga_replay
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artifact_name: B310_REPLAY
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timeout: 720
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max_attempts: 2
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B310_FIFO:
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image_core: b310_fifo_rfnoc_image_core.yml
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target_name: B310
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image_core_name: usrp_b310_fpga_fifo
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artifact_name: B310_FIFO
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timeout: 720
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max_attempts: 2
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- name: b310_reduced_targets_matrix
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type: object
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default:
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B310_REPLAY:
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image_core: b310_replay_rfnoc_image_core.yml
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target_name: B310
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image_core_name: usrp_b310_fpga_replay
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artifact_name: B310_REPLAY
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timeout: 720
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max_attempts: 2
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B310_FIFO:
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image_core: b310_fifo_rfnoc_image_core.yml
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target_name: B310
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image_core_name: usrp_b310_fpga_fifo
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artifact_name: B310_FIFO
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timeout: 720
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max_attempts: 2
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stages:
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### START: B310 stages
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- stage: provide_b310_fpga_images_stage
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displayName: Provide B310 FPGA Images
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dependsOn: analyze_changeset
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variables:
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UhdTestList: $[stageDependencies.analyze_changeset.analyze.outputs['gen_testlist.UhdTestList']]
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BuildRequired: $[or(
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contains(stageDependencies.analyze_changeset.analyze.outputs['gen_testlist.UhdTestList'], 'fpga.usrp3.b310'),
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contains(stageDependencies.analyze_changeset.analyze.outputs['gen_testlist.UhdTestList'], 'fpga.usrp3.all')
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)]
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jobs:
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- template: ../templates/jobs-provide-fpga-artifacts.yml
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parameters:
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id: b310
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device_name: B310
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ip_target: B310_IP
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package_name: b310_fpga_default
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clean_ip_build: ${{ parameters.clean_ip_build }}
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num_ip_jobs: ${{ parameters.num_ip_jobs }}
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publish_int_files: ${{ parameters.publish_int_files }}
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package_and_publish_images: ${{ parameters.package_and_publish_images }}
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package_access: ${{ parameters.package_access }}
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fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
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top_dir: uhddev/fpga/usrp3/top/b300
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target_full_matrix: ${{ parameters.b310_full_targets_matrix }}
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target_reduced_matrix: ${{ parameters.b310_reduced_targets_matrix }}
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### END: B310 stages
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